80 lines
2.5 KiB
Plaintext
80 lines
2.5 KiB
Plaintext
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CORE Generator Options:
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Target Device : xc7k410t-ffg900
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Speed Grade : -2
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HDL : verilog
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Synthesis Tool : Foundation_ISE
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MIG Output Options:
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Module Name : ddr3_interface
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No of Controllers : 1
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Selected Compatible Device(s) : xc7k325t-ffg900
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FPGA Options:
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System Clock Type : Single-Ended
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Reference Clock Type : No Buffer
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Debug Port : ON
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Internal Vref : disabled
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IO Power Reduction : ON
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XADC instantiation in MIG : Enabled
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Extended FPGA Options:
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DCI for DQ,DQS/DQS#,DM : enabled
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Internal Termination (HR Banks) : 50 Ohms
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/*******************************************************/
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/* Controller 0 */
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/*******************************************************/
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Controller Options :
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Memory : DDR3_SDRAM
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Interface : AXI
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Design Clock Frequency : 2000 ps (500.00 MHz)
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Phy to Controller Clock Ratio : 4:1
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Input Clock Period : 10000 ps
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CLKFBOUT_MULT (PLL) : 10
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DIVCLK_DIVIDE (PLL) : 1
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VCC_AUX IO : 1.8V
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Memory Type : Components
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Memory Part : MT41J256m16XX-125
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Equivalent Part(s) : MT41J256M16HA-125
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Data Width : 32
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ECC : Disabled
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Data Mask : enabled
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ORDERING : Normal
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AXI Parameters :
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Data Width : 128
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Arbitration Scheme : ROUND_ROBIN
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Narrow Burst Support : 1
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ID Width : 4
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Memory Options:
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Burst Length (MR0[1:0]) : 8 - Fixed
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Read Burst Type (MR0[3]) : Sequential
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CAS Latency (MR0[6:4]) : 7
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Output Drive Strength (MR1[5,1]) : RZQ/7
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Controller CS option : Enable
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Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/4
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Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
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Memory Address Mapping : BANK_ROW_COLUMN
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Bank Selections:
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System_Clock:
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SignalName: sys_clk_i
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PadLocation: AD17(SRCC_P) Bank: 32
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System_Control:
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SignalName: sys_rst
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PadLocation: No connect Bank: Select Bank
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SignalName: init_calib_complete
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PadLocation: No connect Bank: Select Bank
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SignalName: tg_compare_error
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PadLocation: No connect Bank: Select Bank
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