586 lines
33 KiB
Verilog
586 lines
33 KiB
Verilog
//*****************************************************************************
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// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 1.8
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// \ \ Application : MIG
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// / / Filename : ddr3_interface.veo
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:34:47 $
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// \ \ / \ Date Created : Tue Sept 21 2010
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// \___\/\___\
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//
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// Device : 7 Series
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// Design Name : DDR3 SDRAM
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// Purpose : Template file containing code that can be used as a model
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// for instantiating a CORE Generator module in a HDL design.
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// Revision History :
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//*****************************************************************************
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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ddr3_interface # (
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//***************************************************************************
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// The following parameters refer to width of various ports
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//***************************************************************************
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.BANK_WIDTH (3),
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// # of memory Bank Address bits.
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.CK_WIDTH (1),
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// # of CK/CK# outputs to memory.
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.COL_WIDTH (10),
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// # of memory Column Address bits.
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.CS_WIDTH (1),
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// # of unique CS outputs to memory.
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.nCS_PER_RANK (1),
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// # of unique CS outputs per rank for phy
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.CKE_WIDTH (1),
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// # of CKE outputs to memory.
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.DATA_BUF_ADDR_WIDTH (5),
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.DQ_CNT_WIDTH (5),
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// = ceil(log2(DQ_WIDTH))
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.DQ_PER_DM (8),
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.DM_WIDTH (4),
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// # of DM (data mask)
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.DQ_WIDTH (32),
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// # of DQ (data)
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.DQS_WIDTH (4),
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.DQS_CNT_WIDTH (2),
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// = ceil(log2(DQS_WIDTH))
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.DRAM_WIDTH (8),
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// # of DQ per DQS
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.ECC ("OFF"),
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.DATA_WIDTH (32),
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.ECC_TEST ("OFF"),
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.PAYLOAD_WIDTH (32),
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.ECC_WIDTH (8),
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.MC_ERR_ADDR_WIDTH (31),
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.nBANK_MACHS (4),
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.RANKS (1),
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// # of Ranks.
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.ODT_WIDTH (1),
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// # of ODT outputs to memory.
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.ROW_WIDTH (15),
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// # of memory Row Address bits.
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.ADDR_WIDTH (29),
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// # = RANK_WIDTH + BANK_WIDTH
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// + ROW_WIDTH + COL_WIDTH;
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// Chip Select is always tied to low for
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// single rank devices
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.USE_CS_PORT (1),
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// # = 1, When Chip Select (CS#) output is enabled
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// = 0, When Chip Select (CS#) output is disabled
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// If CS_N disabled, user must connect
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// DRAM CS_N input(s) to ground
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.USE_DM_PORT (1),
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// # = 1, When Data Mask option is enabled
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// = 0, When Data Mask option is disbaled
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// When Data Mask option is disabled in
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// MIG Controller Options page, the logic
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// related to Data Mask should not get
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// synthesized
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.USE_ODT_PORT (1),
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// # = 1, When ODT output is enabled
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// = 0, When ODT output is disabled
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.PHY_CONTROL_MASTER_BANK (1),
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// The bank index where master PHY_CONTROL resides,
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// equal to the PLL residing bank
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//***************************************************************************
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// The following parameters are mode register settings
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//***************************************************************************
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.AL ("0"),
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// DDR3 SDRAM:
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// Additive Latency (Mode Register 1).
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// # = "0", "CL-1", "CL-2".
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// DDR2 SDRAM:
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// Additive Latency (Extended Mode Register).
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.nAL (0),
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// # Additive Latency in number of clock
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// cycles.
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.BURST_MODE ("8"),
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// DDR3 SDRAM:
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// Burst Length (Mode Register 0).
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// # = "8", "4", "OTF".
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// DDR2 SDRAM:
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// Burst Length (Mode Register).
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// # = "8", "4".
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.BURST_TYPE ("SEQ"),
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// DDR3 SDRAM: Burst Type (Mode Register 0).
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// DDR2 SDRAM: Burst Type (Mode Register).
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// # = "SEQ" - (Sequential),
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// = "INT" - (Interleaved).
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.CL (7),
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// in number of clock cycles
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// DDR3 SDRAM: CAS Latency (Mode Register 0).
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// DDR2 SDRAM: CAS Latency (Mode Register).
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.CWL (6),
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// in number of clock cycles
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// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
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// DDR2 SDRAM: Can be ignored
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.OUTPUT_DRV ("HIGH"),
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// Output Driver Impedance Control (Mode Register 1).
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// # = "HIGH" - RZQ/7,
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// = "LOW" - RZQ/6.
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.RTT_NOM ("60"),
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// RTT_NOM (ODT) (Mode Register 1).
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// # = "DISABLED" - RTT_NOM disabled,
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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// = "40" - RZQ/6.
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.RTT_WR ("OFF"),
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// RTT_WR (ODT) (Mode Register 2).
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// # = "OFF" - Dynamic ODT off,
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// = "120" - RZQ/2,
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// = "60" - RZQ/4,
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.ADDR_CMD_MODE ("1T" ),
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// # = "1T", "2T".
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.REG_CTRL ("OFF"),
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// # = "ON" - RDIMMs,
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// = "OFF" - Components, SODIMMs, UDIMMs.
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.CA_MIRROR ("OFF"),
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// C/A mirror opt for DDR3 dual rank
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//***************************************************************************
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// The following parameters are multiplier and divisor factors for PLLE2.
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// Based on the selected design frequency these parameters vary.
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//***************************************************************************
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.CLKIN_PERIOD (10000),
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// Input Clock Period
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.CLKFBOUT_MULT (10),
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// write PLL VCO multiplier
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.DIVCLK_DIVIDE (1),
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// write PLL VCO divisor
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.CLKOUT0_DIVIDE (2),
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// VCO output divisor for PLL output clock (CLKOUT0)
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.CLKOUT1_DIVIDE (2),
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// VCO output divisor for PLL output clock (CLKOUT1)
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.CLKOUT2_DIVIDE (32),
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// VCO output divisor for PLL output clock (CLKOUT2)
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.CLKOUT3_DIVIDE (8),
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// VCO output divisor for PLL output clock (CLKOUT3)
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//***************************************************************************
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// Memory Timing Parameters. These parameters varies based on the selected
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// memory part.
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//***************************************************************************
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.tCKE (5000),
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// memory tCKE paramter in pS.
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.tFAW (30000),
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// memory tRAW paramter in pS.
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.tPRDI (1_000_000),
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// memory tPRDI paramter in pS.
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.tRAS (35000),
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// memory tRAS paramter in pS.
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.tRCD (13750),
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// memory tRCD paramter in pS.
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.tREFI (7800000),
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// memory tREFI paramter in pS.
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.tRFC (300000),
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// memory tRFC paramter in pS.
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.tRP (13750),
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// memory tRP paramter in pS.
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.tRRD (6000),
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// memory tRRD paramter in pS.
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.tRTP (7500),
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// memory tRTP paramter in pS.
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.tWTR (7500),
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// memory tWTR paramter in pS.
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.tZQI (128_000_000),
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// memory tZQI paramter in nS.
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.tZQCS (64),
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// memory tZQCS paramter in clock cycles.
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//***************************************************************************
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// Simulation parameters
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//***************************************************************************
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.SIM_BYPASS_INIT_CAL ("OFF"),
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// # = "OFF" - Complete memory init &
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// calibration sequence
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// # = "SKIP" - Not supported
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// # = "FAST" - Complete memory init & use
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// abbreviated calib sequence
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.SIMULATION ("FALSE"),
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// Should be TRUE during design simulations and
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// FALSE during implementations
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//***************************************************************************
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// The following parameters varies based on the pin out entered in MIG GUI.
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// Do not change any of these parameters directly by editing the RTL.
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// Any changes required should be done through GUI and the design regenerated.
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//***************************************************************************
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.BYTE_LANES_B0 (4'b1111),
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// Byte lanes used in an IO column.
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.BYTE_LANES_B1 (4'b1110),
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// Byte lanes used in an IO column.
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.BYTE_LANES_B2 (4'b0000),
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// Byte lanes used in an IO column.
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.BYTE_LANES_B3 (4'b0000),
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// Byte lanes used in an IO column.
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.BYTE_LANES_B4 (4'b0000),
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// Byte lanes used in an IO column.
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.DATA_CTL_B0 (4'b1111),
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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.DATA_CTL_B1 (4'b0000),
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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.DATA_CTL_B2 (4'b0000),
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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.DATA_CTL_B3 (4'b0000),
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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.DATA_CTL_B4 (4'b0000),
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// Indicates Byte lane is data byte lane
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// or control Byte lane. '1' in a bit
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// position indicates a data byte lane and
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// a '0' indicates a control byte lane
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.PHY_0_BITLANES (48'h3FE_3FE_3FE_2FF),
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.PHY_1_BITLANES (48'h3FF_FFF_C00_000),
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.PHY_2_BITLANES (48'h000_000_000_000),
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.CK_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13),
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.ADDR_MAP (192'h000_139_138_137_136_135_134_133_132_131_130_129_128_127_126_12B),
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.BANK_MAP (36'h12A_125_124),
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.CAS_MAP (12'h122),
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.CKE_ODT_BYTE_MAP (8'h00),
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.CKE_MAP (96'h000_000_000_000_000_000_000_11B),
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.ODT_MAP (96'h000_000_000_000_000_000_000_11A),
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.CS_MAP (120'h000_000_000_000_000_000_000_000_000_120),
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.PARITY_MAP (12'h000),
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.RAS_MAP (12'h123),
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.WE_MAP (12'h121),
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.DQS_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01_02_03),
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.DATA0_MAP (96'h031_032_033_034_035_036_037_038),
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.DATA1_MAP (96'h021_022_023_024_025_026_027_028),
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.DATA2_MAP (96'h011_012_013_014_015_016_017_018),
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.DATA3_MAP (96'h000_001_002_003_004_005_006_007),
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.DATA4_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA5_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA6_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA7_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA8_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA9_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA10_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA11_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA12_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA13_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA14_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA15_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA16_MAP (96'h000_000_000_000_000_000_000_000),
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.DATA17_MAP (96'h000_000_000_000_000_000_000_000),
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.MASK0_MAP (108'h000_000_000_000_000_009_019_029_039),
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.MASK1_MAP (108'h000_000_000_000_000_000_000_000_000),
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.SLOT_0_CONFIG (8'b0000_0001),
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// Mapping of Ranks.
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.SLOT_1_CONFIG (8'b0000_0000),
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// Mapping of Ranks.
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.MEM_ADDR_ORDER ("BANK_ROW_COLUMN"),
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//***************************************************************************
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// IODELAY and PHY related parameters
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//***************************************************************************
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.IODELAY_HP_MODE ("ON"),
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// to phy_top
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.IBUF_LPWR_MODE ("OFF"),
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// to phy_top
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.DATA_IO_IDLE_PWRDWN ("ON"),
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// # = "ON", "OFF"
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.DATA_IO_PRIM_TYPE ("HP_LP"),
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// # = "HP_LP", "HR_LP", "DEFAULT"
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.CKE_ODT_AUX ("FALSE"),
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.USER_REFRESH ("OFF"),
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.WRLVL ("ON"),
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// # = "ON" - DDR3 SDRAM
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// = "OFF" - DDR2 SDRAM.
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.ORDERING ("NORM"),
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// # = "NORM", "STRICT", "RELAXED".
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.CALIB_ROW_ADD (16'h0000),
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// Calibration row address will be used for
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// calibration read and write operations
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.CALIB_COL_ADD (12'h000),
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// Calibration column address will be used for
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// calibration read and write operations
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.CALIB_BA_ADD (3'h0),
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// Calibration bank address will be used for
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// calibration read and write operations
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.TCQ (100),
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.IODELAY_GRP ("IODELAY_MIG"),
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// It is associated to a set of IODELAYs with
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// an IDELAYCTRL that have same IODELAY CONTROLLER
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// clock frequency.
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.SYSCLK_TYPE ("SINGLE_ENDED"),
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// System clock type DIFFERENTIAL or SINGLE_ENDED
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.REFCLK_TYPE ("NO_BUFFER"),
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// Reference clock type DIFFERENTIAL or SINGLE_ENDED
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.CMD_PIPE_PLUS1 ("ON"),
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// add pipeline stage between MC and PHY
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.DRAM_TYPE ("DDR3"),
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.CAL_WIDTH ("HALF"),
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.STARVE_LIMIT (2),
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// # = 2,3,4.
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//***************************************************************************
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// Referece clock frequency parameters
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//***************************************************************************
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.REFCLK_FREQ (200.0),
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// IODELAYCTRL reference clock frequency
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.DIFF_TERM_REFCLK ("TRUE"),
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// Differential Termination for idelay
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// reference clock input pins
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//***************************************************************************
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// System clock frequency parameters
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//***************************************************************************
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.tCK (2000),
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// memory tCK paramter.
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// # = Clock Period in pS.
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.nCK_PER_CLK (4),
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// # of memory CKs per fabric CLK
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.DIFF_TERM_SYSCLK ("TRUE"),
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// Differential Termination for System
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// clock input pins
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//***************************************************************************
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// AXI4 Shim parameters
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//***************************************************************************
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.C_S_AXI_ID_WIDTH (4),
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// Width of all master and slave ID signals.
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// # = >= 1.
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.C_S_AXI_ADDR_WIDTH (32),
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// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
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// M_AXI_ARADDR for all SI/MI slots.
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// # = 32.
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.C_S_AXI_DATA_WIDTH (128),
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// Width of WDATA and RDATA on SI slot.
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// Must be <= APP_DATA_WIDTH.
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// # = 32, 64, 128, 256.
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.C_MC_nCK_PER_CLK (4),
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// Indicates whether to instatiate upsizer
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// Range: 0, 1
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.C_S_AXI_SUPPORTS_NARROW_BURST (1),
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// Indicates whether to instatiate upsizer
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// Range: 0, 1
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.C_RD_WR_ARB_ALGORITHM ("ROUND_ROBIN"),
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// Indicates the Arbitration
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// Allowed values - "TDM", "ROUND_ROBIN",
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// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
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.C_S_AXI_REG_EN0 (20'h00000),
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// C_S_AXI_REG_EN0[00] = Reserved
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// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
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// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
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.C_S_AXI_REG_EN1 (20'h00000),
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// Instatiates register slices after the upsizer.
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// The type of register is specified for each channel
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// in a vector. 4 bits per channel are used.
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// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
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// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
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// Possible values for each channel are:
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//
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// 0 => BYPASS = The channel is just wired through the
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// module.
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// 1 => FWD = The master VALID and payload signals
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// are registrated.
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// 2 => REV = The slave ready signal is registrated
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// 3 => FWD_REV = Both FWD and REV
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// 4 => SLAVE_FWD = All slave side signals and master
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// VALID and payload are registrated.
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// 5 => SLAVE_RDY = All slave side signals and master
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// READY are registrated.
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// 6 => INPUTS = Slave and Master side inputs are
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// registrated.
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// 7 => ADDRESS = Optimized for address channel
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.C_S_AXI_CTRL_ADDR_WIDTH (32),
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// Width of AXI-4-Lite address bus
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.C_S_AXI_CTRL_DATA_WIDTH (32),
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// Width of AXI-4-Lite data buses
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.C_S_AXI_BASEADDR (32'h0000_0000),
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// Base address of AXI4 Memory Mapped bus.
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.C_ECC_ONOFF_RESET_VALUE (1),
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// Controls ECC on/off value at startup/reset
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.C_ECC_CE_COUNTER_WIDTH (8),
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// The external memory to controller clock ratio.
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//***************************************************************************
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// Debug parameters
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//***************************************************************************
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.DEBUG_PORT ("ON"),
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// # = "ON" Enable debug signals/controls.
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// = "OFF" Disable debug signals/controls.
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|
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.RST_ACT_LOW (1)
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// =1 for active low reset,
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// =0 for active high.
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)
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u_ddr3_interface (
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|
|
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// Memory interface ports
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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|
.ddr3_addr (ddr3_addr),
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|
.ddr3_ba (ddr3_ba),
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|
.ddr3_ras_n (ddr3_ras_n),
|
|
.ddr3_cas_n (ddr3_cas_n),
|
|
.ddr3_we_n (ddr3_we_n),
|
|
.ddr3_reset_n (ddr3_reset_n),
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|
.ddr3_ck_p (ddr3_ck_p),
|
|
.ddr3_ck_n (ddr3_ck_n),
|
|
.ddr3_cke (ddr3_cke),
|
|
.ddr3_cs_n (ddr3_cs_n),
|
|
.ddr3_dm (ddr3_dm),
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|
.ddr3_odt (ddr3_odt),
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|
.sys_clk_i (sys_clk_i),
|
|
// Application interface ports
|
|
.ui_clk (ui_clk),
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|
.ui_clk_sync_rst (ui_clk_sync_rst),
|
|
.aresetn (aresetn),
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|
.app_sr_req (app_sr_req),
|
|
.app_sr_active (app_sr_active),
|
|
.app_ref_req (app_ref_req),
|
|
.app_ref_ack (app_ref_ack),
|
|
.app_zq_req (app_zq_req),
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|
.app_zq_ack (app_zq_ack),
|
|
|
|
// Slave Interface Write Address Ports
|
|
.s_axi_awid (s_axi_awid),
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|
.s_axi_awaddr (s_axi_awaddr),
|
|
.s_axi_awlen (s_axi_awlen),
|
|
.s_axi_awsize (s_axi_awsize),
|
|
.s_axi_awburst (s_axi_awburst),
|
|
.s_axi_awlock (s_axi_awlock),
|
|
.s_axi_awcache (s_axi_awcache),
|
|
.s_axi_awprot (s_axi_awprot),
|
|
.s_axi_awqos (s_axi_awqos),
|
|
.s_axi_awvalid (s_axi_awvalid),
|
|
.s_axi_awready (s_axi_awready),
|
|
// Slave Interface Write Data Ports
|
|
.s_axi_wdata (s_axi_wdata),
|
|
.s_axi_wstrb (s_axi_wstrb),
|
|
.s_axi_wlast (s_axi_wlast),
|
|
.s_axi_wvalid (s_axi_wvalid),
|
|
.s_axi_wready (s_axi_wready),
|
|
// Slave Interface Write Response Ports
|
|
.s_axi_bready (s_axi_bready),
|
|
.s_axi_bid (s_axi_bid),
|
|
.s_axi_bresp (s_axi_bresp),
|
|
.s_axi_bvalid (s_axi_bvalid),
|
|
// Slave Interface Read Address Ports
|
|
.s_axi_arid (s_axi_arid),
|
|
.s_axi_araddr (s_axi_araddr),
|
|
.s_axi_arlen (s_axi_arlen),
|
|
.s_axi_arsize (s_axi_arsize),
|
|
.s_axi_arburst (s_axi_arburst),
|
|
.s_axi_arlock (s_axi_arlock),
|
|
.s_axi_arcache (s_axi_arcache),
|
|
.s_axi_arprot (s_axi_arprot),
|
|
.s_axi_arqos (s_axi_arqos),
|
|
.s_axi_arvalid (s_axi_arvalid),
|
|
.s_axi_arready (s_axi_arready),
|
|
// Slave Interface Read Data Ports
|
|
.s_axi_rready (s_axi_rready),
|
|
.s_axi_rid (s_axi_rid),
|
|
.s_axi_rdata (s_axi_rdata),
|
|
.s_axi_rresp (s_axi_rresp),
|
|
.s_axi_rlast (s_axi_rlast),
|
|
.s_axi_rvalid (s_axi_rvalid),
|
|
// AXI CTRL port
|
|
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
|
|
.s_axi_ctrl_awready (s_axi_ctrl_awready),
|
|
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
|
|
// Slave Interface Write Data Ports
|
|
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
|
|
.s_axi_ctrl_wready (s_axi_ctrl_wready),
|
|
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
|
|
// Slave Interface Write Response Ports
|
|
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
|
|
.s_axi_ctrl_bready (s_axi_ctrl_bready),
|
|
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
|
|
// Slave Interface Read Address Ports
|
|
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
|
|
.s_axi_ctrl_arready (s_axi_ctrl_arready),
|
|
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
|
|
// Slave Interface Read Data Ports
|
|
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
|
|
.s_axi_ctrl_rready (s_axi_ctrl_rready),
|
|
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
|
|
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
|
|
// Interrupt output
|
|
.interrupt (interrupt),
|
|
.init_calib_complete (init_calib_complete),
|
|
.sys_rst (sys_rst)
|
|
);
|
|
|
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
|
|
|
// You must compile the wrapper file ddr3_interface.v when simulating
|
|
// the core, ddr3_interface. When compiling the wrapper file, be sure to
|
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
|
// instructions, please refer to the "CORE Generator Help".
|