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b210-k7-fpga/top/x300/coregen/coregen.cgp
T
Ben Hilburn 85ad83d8d3 fpga: Updating FPGA code for UHD-3.7.2-rc1
Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
2014-07-22 15:49:02 -07:00

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET package = ffg900
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false