Files
b210-k7-fpga/top/x300/coregen/bus_clk_gen.gise
T
Ben Hilburn 5a525c84f5 fpga: updating b200 and x300 FPGA source code for latest images
Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
2014-05-14 11:42:19 -07:00

32 lines
1.2 KiB
XML

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="bus_clk_gen.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="bus_clk_gen.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="bus_clk_gen.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>