50 lines
1.0 KiB
Batchfile
Executable File
50 lines
1.0 KiB
Batchfile
Executable File
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rem Clean up the results directory
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rmdir /S /Q results
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mkdir results
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rem Synthesize the VHDL Wrapper Files
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echo 'Synthesizing example design with XST';
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xst -ifn xst.scr
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copy bootram_exdes.ngc .\results\
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rem Copy the netlist generated by Coregen
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echo 'Copying files from the netlist directory to the results directory'
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copy ..\..\bootram.ngc results\
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rem Copy the constraints files generated by Coregen
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echo 'Copying files from constraints directory to results directory'
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copy ..\example_design\bootram_exdes.ucf results\
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cd results
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echo 'Running ngdbuild'
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ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
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echo 'Running map'
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map bootram_exdes -o mapped.ncd -pr i
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echo 'Running par'
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par mapped.ncd routed.ncd
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echo 'Running trce'
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trce -e 10 routed.ncd mapped.pcf -o routed
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echo 'Running design through bitgen'
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bitgen -w routed -g UnconstrainedPins:Allow
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echo 'Running netgen to create gate level Verilog model'
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netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
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