47 lines
1.4 KiB
VHDL
47 lines
1.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.zpupkg.all;
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use work.zpu_config.all;
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use work.wishbone_pkg.all;
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package zpu_top_pkg is
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component zpu_wb_bridge is
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port ( -- Native ZPU interface
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clk : in std_logic;
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areset : in std_logic;
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mem_req : in std_logic;
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mem_we : in std_logic;
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mem_ack : out std_logic;
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mem_read : out std_logic_vector(wordSize-1 downto 0);
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mem_write : in std_logic_vector(wordSize-1 downto 0);
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out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
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mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
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-- Wishbone from ZPU
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zpu_wb_i : in wishbone_bus_out;
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zpu_wb_o : out wishbone_bus_in);
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end component;
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component zpu_system is
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generic(
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simulate : boolean := false);
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port ( areset : in std_logic;
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cpu_clk : in std_logic;
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-- ZPU Control signals
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enable : in std_logic;
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interrupt : in std_logic;
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zpu_status : out std_logic_vector(63 downto 0);
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-- wishbone interfaces
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zpu_wb_i : in wishbone_bus_out;
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zpu_wb_o : out wishbone_bus_in);
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end component;
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end zpu_top_pkg;
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