39 lines
665 B
Verilog
39 lines
665 B
Verilog
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module ip_hdr_checksum_tb();
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initial $dumpfile("ip_hdr_checksum_tb.vcd");
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initial $dumpvars(0,ip_hdr_checksum_tb);
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reg clk;
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wire [159:0] in = {
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16'h4500,
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16'h0030,
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16'h4422,
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16'h4000,
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16'h8006,
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16'h0000,
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16'h8c7c,
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16'h19ac,
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16'hae24,
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16'h1e2b
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};
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wire [15:0] out;
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ip_hdr_checksum ip_hdr_checksum
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(.clk(clk),
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.in(in),
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.out(out));
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initial
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begin
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clk <= 0;
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#100 clk <= 1;
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#100 clk <= 0;
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#100 clk <= 1;
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#100 $display("Computed 0x%x, should be 0x442e", out);
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#100 $finish;
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end
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endmodule // ip_hdr_checksum_tb
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