76 lines
1.8 KiB
Verilog
76 lines
1.8 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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//
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module cic_interp
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#(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
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(input clock,
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input reset,
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input enable,
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input [7:0] rate,
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input strobe_in,
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input strobe_out,
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input [bw-1:0] signal_in,
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output reg [bw-1:0] signal_out);
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integer i;
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localparam maxbitgain = (N-1)*log2_of_max_rate;
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wire [bw+maxbitgain-1:0] signal_in_ext;
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reg [bw+maxbitgain-1:0] integrator [0:N-1];
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reg [bw+maxbitgain-1:0] differentiator [0:N-1];
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reg [bw+maxbitgain-1:0] pipeline [0:N-1];
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sign_extend #(bw,bw+maxbitgain)
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ext_input (.in(signal_in),.out(signal_in_ext));
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//FIXME Note that this section has pipe and diff reversed
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// It still works, but is confusing
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always @(posedge clock)
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if(reset | ~enable)
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for(i=0;i<N;i=i+1)
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integrator[i] <= 0;
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else if (enable & strobe_out)
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begin
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if(strobe_in)
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integrator[0] <= integrator[0] + pipeline[N-1];
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for(i=1;i<N;i=i+1)
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integrator[i] <= integrator[i] + integrator[i-1];
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end
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always @(posedge clock)
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if(reset | ~enable)
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begin
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for(i=0;i<N;i=i+1)
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begin
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differentiator[i] <= 0;
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pipeline[i] <= 0;
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end
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end
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else if (enable && strobe_in)
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begin
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differentiator[0] <= signal_in_ext;
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pipeline[0] <= signal_in_ext - differentiator[0];
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for(i=1;i<N;i=i+1)
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begin
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differentiator[i] <= pipeline[i-1];
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pipeline[i] <= pipeline[i-1] - differentiator[i];
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end
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end
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wire [bw-1:0] signal_out_unreg;
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cic_int_shifter #(bw)
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cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
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always @(posedge clock)
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signal_out <= signal_out_unreg;
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endmodule // cic_interp
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