13 lines
316 B
Verilog
13 lines
316 B
Verilog
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module add2_and_clip
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#(parameter WIDTH=16)
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(input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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output [WIDTH-1:0] sum);
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wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
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clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
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(.in(sum_int),.out(sum));
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endmodule // add2_and_clip
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