adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
46 lines
2.2 KiB
Systemverilog
46 lines
2.2 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfdc_timing_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// NCO_RESET_REG : 0x0 (rfdc_timing_control.v)
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// GEARBOX_RESET_REG : 0x4 (rfdc_timing_control.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group RFDC_TIMING_REGS
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//===============================================================================
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// NCO_RESET_REG Register (from rfdc_timing_control.v)
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localparam NCO_RESET_REG = 'h0; // Register Offset
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localparam NCO_RESET_REG_SIZE = 32; // register width in bits
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localparam NCO_RESET_REG_MASK = 32'h3;
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localparam NCO_RESET_START_SIZE = 1; //NCO_RESET_REG:NCO_RESET_START
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localparam NCO_RESET_START_MSB = 0; //NCO_RESET_REG:NCO_RESET_START
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localparam NCO_RESET_START = 0; //NCO_RESET_REG:NCO_RESET_START
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localparam NCO_RESET_DONE_SIZE = 1; //NCO_RESET_REG:NCO_RESET_DONE
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localparam NCO_RESET_DONE_MSB = 1; //NCO_RESET_REG:NCO_RESET_DONE
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localparam NCO_RESET_DONE = 1; //NCO_RESET_REG:NCO_RESET_DONE
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// GEARBOX_RESET_REG Register (from rfdc_timing_control.v)
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localparam GEARBOX_RESET_REG = 'h4; // Register Offset
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localparam GEARBOX_RESET_REG_SIZE = 32; // register width in bits
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localparam GEARBOX_RESET_REG_MASK = 32'h3;
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localparam ADC_RESET_SIZE = 1; //GEARBOX_RESET_REG:ADC_RESET
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localparam ADC_RESET_MSB = 0; //GEARBOX_RESET_REG:ADC_RESET
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localparam ADC_RESET = 0; //GEARBOX_RESET_REG:ADC_RESET
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localparam DAC_RESET_SIZE = 1; //GEARBOX_RESET_REG:DAC_RESET
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localparam DAC_RESET_MSB = 1; //GEARBOX_RESET_REG:DAC_RESET
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localparam DAC_RESET = 1; //GEARBOX_RESET_REG:DAC_RESET
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