Wade Fife 4baf8139c8 fpga: tools: Add modelsim.ini to ModelSim calls ...

This adds the MSIM_VIV_COMPLIBDIR environment variable to specify
a non-default location for the compilation libraries.

This also allows a modelsim.ini other than the one in the ModelSim
installation folder to be used. By default, the one in the simulation
libraries compilation directory will be used. This can be changed by
setting MSIM_MODELSIM_INI to the one you want to use, or set it to an
empty string to use the one in the ModelSim installation folder.


Original-commit: 08473776b28a949027ec8cf2596d8d1b438b979b

2021-06-17 08:16:59 -05:00

..

check_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

git-hash.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ise_jtag_program.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_modelsim.sh

fpga: tools: Add modelsim.ini to ModelSim calls

2021-06-17 08:16:59 -05:00

launch_vivado.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

launch_vivado.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_vlint.sh

fpga: tools: Add modelsim.ini to ModelSim calls

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setupenv_base.sh

fpga: tools: Add modelsim.ini to ModelSim calls

2021-06-17 08:16:59 -05:00

shared-ip-loc-manage.sh

Merge FPGA repository back into UHD repository

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viv_check_syntax.tcl

Merge FPGA repository back into UHD repository

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viv_gen_ip_makefile.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_gen_part_id.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_generate_bd.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_hls_ip.tcl

fpga: tools: Fix HLS IP build with Cygwin

2020-05-12 13:47:20 -05:00

viv_generate_ip.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_patch_ip.tcl

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

viv_hardware_utils.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_ip_utils.tcl

fpga: tools: Ignore BD layout info for TCL-based BD

2020-03-12 10:33:24 -05:00

viv_ip_xci_editor.py

fpga: tools: Add support for RFSoC

2021-06-03 10:22:04 -05:00

viv_sim_project.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

viv_strategies.tcl

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

viv_synth.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_utils.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

xil_bitfile_parser.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00