5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
445 lines
18 KiB
Verilog
445 lines
18 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: db_gpio_interface
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//
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// Description:
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// Interface for GPIO interface towards FBX daughterboards.
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//
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//
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// The 20 available GPIO lines are assigned with
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// - 12x RF switches(3x per channel)
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// - 2x I2C to Sync switches IO Expander
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// - 6x empty
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//
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`default_nettype none
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module db_gpio_interface #(
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parameter LED_REGISTER_ADDRESS = 0
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) (
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// Clocks and reset
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input wire radio_clk,
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input wire pll_ref_clk,
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input wire in_sync_clk,
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output wire out_sync_clk,
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// DB state lines (domain: radio_clk)
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input wire [ 7:0] db_state,
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// Request (domain: radio_clk)
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input wire ctrlport_rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response (domain: radio_clk)
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// ControlPort request to CPLD (domain: radio_clk)
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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// ControlPort response from CPLD (domain: radio_clk)
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// GPIO interface (domain: pll_ref_clk)
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input wire [19:0] gpio_in,
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output wire [19:0] gpio_out,
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output wire [19:0] gpio_out_en,
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// Version (Constant)
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output wire [95:0] version_info
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);
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`include "../../regmap/x440/versioning_regs_regmap_utils.vh"
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`include "regmap/fbx_ctrl_regmap_utils.vh"
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`include "../../regmap/versioning_utils.vh"
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//----------------------------------------------------------------------------
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// Radio_clk -> pll_ref_clk clock crossing
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//----------------------------------------------------------------------------
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wire ctrlport_rst_prc;
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wire ctrlport_req_wr_prc;
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wire ctrlport_req_rd_prc;
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wire [19:0] ctrlport_req_addr_prc;
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wire [31:0] ctrlport_req_data_prc;
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wire ctrlport_resp_ack_prc;
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wire [ 1:0] ctrlport_resp_status_prc;
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wire [31:0] ctrlport_resp_data_prc;
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ctrlport_clk_cross core_clk_cross_slave (
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.rst (ctrlport_rst),
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.s_ctrlport_clk (radio_clk),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_portid (),
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.s_ctrlport_req_rem_epid (),
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.s_ctrlport_req_rem_portid (),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (),
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.s_ctrlport_req_has_time (),
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.s_ctrlport_req_time (),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_clk (pll_ref_clk),
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.m_ctrlport_req_wr (ctrlport_req_wr_prc),
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.m_ctrlport_req_rd (ctrlport_req_rd_prc),
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.m_ctrlport_req_addr (ctrlport_req_addr_prc),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (ctrlport_req_data_prc),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (ctrlport_resp_ack_prc),
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.m_ctrlport_resp_status (ctrlport_resp_status_prc),
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.m_ctrlport_resp_data (ctrlport_resp_data_prc)
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);
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reset_sync reset_sync_prc (
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.clk (pll_ref_clk),
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.reset_in (ctrlport_rst),
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.reset_out (ctrlport_rst_prc)
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);
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wire [7:0] db_state_prc;
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handshake #(
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.WIDTH (8)
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) synchronizer_db_state (
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.clk_a (radio_clk),
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.rst_a (ctrlport_rst),
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.valid_a (1'b1),
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.data_a (db_state),
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.busy_a (),
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.clk_b (pll_ref_clk),
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.valid_b (),
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.data_b (db_state_prc)
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);
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//----------------------------------------------------------------------------
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// CtrlPort Splitter
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//----------------------------------------------------------------------------
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wire [19:0] rf_atr_ctrlport_req_addr;
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wire [31:0] rf_atr_ctrlport_req_data;
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wire rf_atr_ctrlport_req_rd;
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wire rf_atr_ctrlport_req_wr;
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wire rf_atr_ctrlport_resp_ack;
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wire [31:0] rf_atr_ctrlport_resp_data;
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wire [ 1:0] rf_atr_ctrlport_resp_status;
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wire [19:0] sync_ctrlport_req_addr;
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wire [31:0] sync_ctrlport_req_data;
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wire sync_ctrlport_req_rd;
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wire sync_ctrlport_req_wr;
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wire sync_ctrlport_resp_ack;
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wire [31:0] sync_ctrlport_resp_data;
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wire [ 1:0] sync_ctrlport_resp_status;
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wire [19:0] led_atr_ctrlport_req_addr;
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wire [31:0] led_atr_ctrlport_req_data;
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wire led_atr_ctrlport_req_rd;
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wire led_atr_ctrlport_req_wr;
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wire led_atr_ctrlport_resp_ack;
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wire [31:0] led_atr_ctrlport_resp_data;
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wire [ 1:0] led_atr_ctrlport_resp_status;
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wire [19:0] clk_en_ctrlport_req_addr;
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wire [31:0] clk_en_ctrlport_req_data;
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wire clk_en_ctrlport_req_rd;
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wire clk_en_ctrlport_req_wr;
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wire clk_en_ctrlport_resp_ack;
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wire [31:0] clk_en_ctrlport_resp_data;
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wire [ 1:0] clk_en_ctrlport_resp_status;
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ctrlport_splitter #(
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.NUM_SLAVES (4)
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) fbx_ctrlport_splitter (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (ctrlport_req_wr_prc),
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.s_ctrlport_req_rd (ctrlport_req_rd_prc),
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.s_ctrlport_req_addr (ctrlport_req_addr_prc),
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.s_ctrlport_req_data (ctrlport_req_data_prc),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
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.s_ctrlport_resp_status (ctrlport_resp_status_prc),
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.s_ctrlport_resp_data (ctrlport_resp_data_prc),
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.m_ctrlport_req_wr ({ clk_en_ctrlport_req_wr, led_atr_ctrlport_req_wr, sync_ctrlport_req_wr, rf_atr_ctrlport_req_wr }),
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.m_ctrlport_req_rd ({ clk_en_ctrlport_req_rd, led_atr_ctrlport_req_rd, sync_ctrlport_req_rd, rf_atr_ctrlport_req_rd }),
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.m_ctrlport_req_addr ({ clk_en_ctrlport_req_addr, led_atr_ctrlport_req_addr, sync_ctrlport_req_addr, rf_atr_ctrlport_req_addr }),
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.m_ctrlport_req_data ({ clk_en_ctrlport_req_data, led_atr_ctrlport_req_data, sync_ctrlport_req_data, rf_atr_ctrlport_req_data }),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack ({ clk_en_ctrlport_resp_ack, led_atr_ctrlport_resp_ack, sync_ctrlport_resp_ack, rf_atr_ctrlport_resp_ack }),
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.m_ctrlport_resp_status ({ clk_en_ctrlport_resp_status, led_atr_ctrlport_resp_status, sync_ctrlport_resp_status, rf_atr_ctrlport_resp_status }),
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.m_ctrlport_resp_data ({ clk_en_ctrlport_resp_data, led_atr_ctrlport_resp_data, sync_ctrlport_resp_data, rf_atr_ctrlport_resp_data })
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);
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//----------------------------------------------------------------------------
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// Switch Control
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//----------------------------------------------------------------------------
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wire rf0_tx_rx_rfs, rf0_rx_rfs, rf0_tdds;
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wire rf1_tx_rx_rfs, rf1_rx_rfs, rf1_tdds;
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wire rf2_tx_rx_rfs, rf2_rx_rfs, rf2_tdds;
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wire rf3_tx_rx_rfs, rf3_rx_rfs, rf3_tdds;
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rf_atr_control #(
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.REG_BASE (RF_ATR_REGS),
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.REG_SIZE (RF_ATR_REGS_SIZE)
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) rf_atr_control_i (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (rf_atr_ctrlport_req_wr),
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.s_ctrlport_req_rd (rf_atr_ctrlport_req_rd),
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.s_ctrlport_req_addr (rf_atr_ctrlport_req_addr),
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.s_ctrlport_req_data (rf_atr_ctrlport_req_data),
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.s_ctrlport_resp_ack (rf_atr_ctrlport_resp_ack),
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.s_ctrlport_resp_status (rf_atr_ctrlport_resp_status),
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.s_ctrlport_resp_data (rf_atr_ctrlport_resp_data),
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.db_state (db_state_prc),
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.rf0_tx_rx_rfs (rf0_tx_rx_rfs),
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.rf0_rx_rfs (rf0_rx_rfs),
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.rf0_tdds (rf0_tdds),
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.rf1_tx_rx_rfs (rf1_tx_rx_rfs),
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.rf1_rx_rfs (rf1_rx_rfs),
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.rf1_tdds (rf1_tdds),
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.rf2_tx_rx_rfs (rf2_tx_rx_rfs),
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.rf2_rx_rfs (rf2_rx_rfs),
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.rf2_tdds (rf2_tdds),
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.rf3_tx_rx_rfs (rf3_tx_rx_rfs),
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.rf3_rx_rfs (rf3_rx_rfs),
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.rf3_tdds (rf3_tdds)
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);
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//----------------------------------------------------------------------------
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// LED Control
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//----------------------------------------------------------------------------
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wire cpld_ctrlport_req_wr;
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wire cpld_ctrlport_req_rd;
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wire [19:0] cpld_ctrlport_req_addr;
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wire [31:0] cpld_ctrlport_req_data;
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wire [ 3:0] cpld_ctrlport_req_byte_en;
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wire cpld_ctrlport_resp_ack;
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wire [ 1:0] cpld_ctrlport_resp_status;
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wire [31:0] cpld_ctrlport_resp_data;
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led_atr_control #(
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.LED_REGISTER_ADDRESS (LED_REGISTER_ADDRESS),
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.REG_BASE (LED_ATR_REGS),
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.REG_SIZE (LED_ATR_REGS_SIZE)
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) led_atr_control_i (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (led_atr_ctrlport_req_wr),
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.s_ctrlport_req_rd (led_atr_ctrlport_req_rd),
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.s_ctrlport_req_addr (led_atr_ctrlport_req_addr),
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.s_ctrlport_req_data (led_atr_ctrlport_req_data),
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.s_ctrlport_resp_ack (led_atr_ctrlport_resp_ack),
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.s_ctrlport_resp_status (led_atr_ctrlport_resp_status),
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.s_ctrlport_resp_data (led_atr_ctrlport_resp_data),
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.db_state (db_state_prc),
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.m_ctrlport_req_wr (cpld_ctrlport_req_wr),
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.m_ctrlport_req_rd (cpld_ctrlport_req_rd),
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.m_ctrlport_req_addr (cpld_ctrlport_req_addr),
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.m_ctrlport_req_data (cpld_ctrlport_req_data),
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.m_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en),
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.m_ctrlport_resp_ack (cpld_ctrlport_resp_ack),
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.m_ctrlport_resp_status (cpld_ctrlport_resp_status),
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.m_ctrlport_resp_data (cpld_ctrlport_resp_data)
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);
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ctrlport_clk_cross core_clk_cross_cpld_master (
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.rst (ctrlport_rst_prc),
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.s_ctrlport_clk (pll_ref_clk),
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.s_ctrlport_req_wr (cpld_ctrlport_req_wr),
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.s_ctrlport_req_rd (cpld_ctrlport_req_rd),
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.s_ctrlport_req_addr (cpld_ctrlport_req_addr),
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.s_ctrlport_req_portid (),
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.s_ctrlport_req_rem_epid (),
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.s_ctrlport_req_rem_portid (),
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.s_ctrlport_req_data (cpld_ctrlport_req_data),
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.s_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (),
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.s_ctrlport_req_time (),
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.s_ctrlport_resp_ack (cpld_ctrlport_resp_ack),
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.s_ctrlport_resp_status (cpld_ctrlport_resp_status),
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.s_ctrlport_resp_data (cpld_ctrlport_resp_data),
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.m_ctrlport_clk (radio_clk),
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.m_ctrlport_req_wr (m_ctrlport_req_wr),
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.m_ctrlport_req_rd (m_ctrlport_req_rd),
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.m_ctrlport_req_addr (m_ctrlport_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (m_ctrlport_req_data),
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.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
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.m_ctrlport_resp_status (m_ctrlport_resp_status),
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.m_ctrlport_resp_data (m_ctrlport_resp_data)
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);
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//----------------------------------------------------------------------------
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// I2C Control
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//----------------------------------------------------------------------------
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wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o;
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wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o;
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ctrlport_to_i2c_sync_ctrl #(
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.BASE_ADDRESS(RF_SYNC_REGS),
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.PRESCALE(1000)
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) ctrlport_to_i2c_inst (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (sync_ctrlport_req_wr),
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.s_ctrlport_req_rd (sync_ctrlport_req_rd),
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.s_ctrlport_req_addr (sync_ctrlport_req_addr),
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.s_ctrlport_req_data (sync_ctrlport_req_data),
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.s_ctrlport_resp_ack (sync_ctrlport_resp_ack),
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.s_ctrlport_resp_status (sync_ctrlport_resp_status),
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.s_ctrlport_resp_data (sync_ctrlport_resp_data),
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.scl_pad_i (i2c_scl_i),
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.scl_pad_o (i2c_scl_o),
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.scl_pad_en_o (i2c_scl_en_o),
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.sda_pad_i (i2c_sda_i),
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.sda_pad_o (i2c_sda_o),
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.sda_pad_en_o (i2c_sda_en_o)
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);
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//----------------------------------------------------------------------------
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// Sync Clock Enable
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//----------------------------------------------------------------------------
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clock_en_control #(
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.BASE_ADDRESS(SYNC_CLK_EN_REGS)
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) clock_en_control_inst (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (clk_en_ctrlport_req_wr),
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.s_ctrlport_req_rd (clk_en_ctrlport_req_rd),
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.s_ctrlport_req_addr (clk_en_ctrlport_req_addr),
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.s_ctrlport_req_data (clk_en_ctrlport_req_data),
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.s_ctrlport_resp_ack (clk_en_ctrlport_resp_ack),
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.s_ctrlport_resp_status (clk_en_ctrlport_resp_status),
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.s_ctrlport_resp_data (clk_en_ctrlport_resp_data),
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.clk_in (in_sync_clk),
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.clk_out (out_sync_clk)
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);
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//----------------------------------------------------------------------------
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// wire assignment
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//----------------------------------------------------------------------------
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// RFS1, RFS2, RFS3, RFS4, RFS5, RFS6, RFS7, RFS8, TDDS1, TDDS2, TDDS3, TDDS4,
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// 2 unused, 2 for I2C, 4 unused.
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assign i2c_sda_i = gpio_in[4];
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assign i2c_scl_i = gpio_in[5];
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assign gpio_out = {rf0_tx_rx_rfs, rf0_rx_rfs,
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rf1_tx_rx_rfs, rf1_rx_rfs,
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rf2_tx_rx_rfs, rf2_rx_rfs,
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rf3_tx_rx_rfs, rf3_rx_rfs,
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rf0_tdds, rf1_tdds,
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rf2_tdds, rf3_tdds,
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2'b0, // Unused
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i2c_scl_o, i2c_sda_o, // I2C
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4'b0 // Unused
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};
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assign gpio_out_en = {12'hFFF, // Switches
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2'b0, // Unused
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~i2c_scl_en_o, ~i2c_sda_en_o, // I2C enables tri-state when HIGH
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4'b0 // Unused
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};
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//----------------------------------------------------------------------------
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// version_info
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//----------------------------------------------------------------------------
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// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
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assign version_info = build_component_versions(
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DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
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build_version(
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DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
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DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
|
|
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
|
|
build_version(
|
|
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
|
|
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
|
|
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
|
|
|
|
endmodule
|
|
|
|
`default_nettype wire
|
|
|
|
//XmlParse xml_on
|
|
//<regmap name="VERSIONING_REGS_REGMAP">
|
|
// <group name="VERSIONING_CONSTANTS">
|
|
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
|
|
// <info>
|
|
// Daughterboard GPIO interface.{BR/}
|
|
// For guidance on when to update these revision numbers,
|
|
// please refer to the register map documentation accordingly:
|
|
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
|
|
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
|
|
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
|
|
// </info>
|
|
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
|
|
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
|
|
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
|
|
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
|
|
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
|
|
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
|
|
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x22070116"/>
|
|
// </enumeratedtype>
|
|
// </group>
|
|
//</regmap>
|
|
|
|
//<regmap name="FBX_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
|
// <info>
|
|
// This map contains register windows for controlling the different sources
|
|
// that drive the state of FBX control lines.
|
|
// </info>
|
|
// <group name="FBX_CONTROLS">
|
|
// <window name="RF_ATR_REGS" offset="0x0" size="0x2000" targetregmap="RF_ATR_REGMAP">
|
|
// <info>Control RF switches in FBX daughterboard based on the ATR state of the accessed radio</info>
|
|
// </window>
|
|
// <window name="RF_SYNC_REGS" offset="0x2000" size="0x2000" targetregmap="RF_SYNC_REGMAP">
|
|
// <info>I2C interface to FBX daughterboard IO Expander that controls SYNC switches and rfs en</info>
|
|
// </window>
|
|
// <window name="LED_ATR_REGS" offset="0x4000" size="0x2000" targetregmap="LED_ATR_REGMAP">
|
|
// <info>Control TX/RX LEDs based on the ATR state of the accessed radio</info>
|
|
// </window>
|
|
// <window name="SYNC_CLK_EN_REGS" offset="0x6000" size="0x2000" targetregmap="CLK_EN_REGMAP">
|
|
// <info>Clock enable register for SYNC INJECT 5 MHz clock</info>
|
|
// </window>
|
|
// </group>
|
|
//</regmap>
|
|
//XmlParse xml_off
|