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Wade Fife d16d1e121c fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin 
Original-commit: 7f5f771796de590c4ed4bba7b09cda3a906535c6
2020-06-12 15:50:16 -05:00
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coregen_dsp
Merge FPGA repository back into UHD repository
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dboards
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doc
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dts
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ip
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sim
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.gitignore
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build_n3xx.tcl
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dev_config.json
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Makefile
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Makefile.n3xx.inc
fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin
2020-06-12 15:50:16 -05:00
mb_clocks.xdc
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mb_pins.xdc
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mb_timing.xdc
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n3xx_clocking.v
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n3xx_core.v
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n3xx_db_fe_core.v
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n3xx_mgt_channel_wrapper.v
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n3xx_mgt_io_core.v
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n3xx_mgt_wrapper.v
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n3xx_serial_dac_arb.vhd
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n3xx_serial_dac.vhd
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n3xx_wr_top.vhd
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n3xx_wr.xdc
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n300_bist_image_core.v
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n300_bist_image_core.yml
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n300_bist_static_router.hex
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n300_rfnoc_image_core.v
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n300_rfnoc_image_core.yml
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n300_static_router.hex
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n310_1ge.xdc
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n310_10ge.xdc
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n310_aurora.xdc
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n310_bist_image_core.v
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n310_bist_image_core.yml
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n310_bist_static_router.hex
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n310_dram.xdc
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n310_rfnoc_image_core.v
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n310_rfnoc_image_core.yml
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n310_static_router.hex
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n320_rfnoc_image_core.v
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n320_rfnoc_image_core.yml
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n320_static_router.hex
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setupenv.sh
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WrapBufg.vhd
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