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Wade Fife dcbc6a9c78 fpga: tools: Add default Vivado install location 
Xilinx changed the default Vivado install location from /opt/Xilix to
/tools/Xilinx. This commit adds support for finding Vivado in either
the new location or the old location.


Original-commit: 156d714b8fb288100d242ea200ae1d1dcd6bcd57
2020-04-01 08:45:41 -05:00
..
auto_inst_e310.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
auto_inst_x310.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
check_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
git-hash.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ise_jtag_program.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vivado.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vivado.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv_base.sh
fpga: tools: Add default Vivado install location
2020-04-01 08:45:41 -05:00
shared-ip-loc-manage.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
uhd_image_builder_gui.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
uhd_image_builder.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_check_syntax.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_ip_makefile.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_part_id.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_bd.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_hls_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_hardware_utils.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_ip_utils.tcl
fpga: tools: Ignore BD layout info for TCL-based BD
2020-03-12 10:33:24 -05:00
viv_ip_xci_editor.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_sim_project.tcl
fpga: tools: Add modelsim to make sim targets
2020-03-20 10:34:59 -05:00
viv_strategies.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_synth.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_utils.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xil_bitfile_parser.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00