379 lines
14 KiB
Verilog
379 lines
14 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_resize
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//
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// Description:
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//
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// Takes a CHDR packet data stream and converts it from one CHDR width to a
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// different CHDR width. It can also do CHDR width conversion without
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// changing the bus width, if the bus width is the same size as the smaller
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// CHDR width.
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//
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// For example, to convert from a 64-bit CHDR_W to a 256-bit CHDR_W, you
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// would set I_CHDR_W to 64 and O_CHDR_W to 256 (by default, I_DATA_W will be
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// set to 64 and O_DATA_W will be set to 256).
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//
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// But you could also convert from 64-bit CHDR to 256-bit CHDR while keeping
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// the bus width at 64 bits. In this case you would set I_CHDR_W to 64 and
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// O_CHDR_W to 256, but set both I_DATA_W and O_DATA_W to 64.
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//
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// There are some restrictions, including the requirement that I_CHDR_W ==
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// I_DATA_W or O_CHDR_W == O_DATA_W, and that MIN(I_DATA_W, O_DATA_W) ==
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// MIN(I_CHDR_W, O_CHDR_W). Basically, it can't do CHDR width conversion
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// where the smaller CHDR width is smaller than the bus width(s). For
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// example, you could not do conversion from 64-bit to 256-bit CHDR with
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// input and output bus widths of 256.
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//
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// TUSER is supported, but is not resized. TUSER is sampled along with the
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// first word of the input packet and is assumed to be the same for the
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// duration of the packet.
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//
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// Also, note that packets with different CHDR_W have a different maximum
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// number of metadata bytes. This module repacks the metadata in
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// little-endian order in the new word size. If there is too much metadata
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// for a smaller CHDR_W packet, the extra data will be discarded.
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//
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// Parameters:
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//
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// I_CHDR_W : CHDR_W for the input data stream on i_chdr.
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// O_CHDR_W : CHDR_W for the output data stream on o_chdr.
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// I_DATA_W : Bus width for i_chdr_tdata.
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// O_DATA_W : Bus width for o_chdr_tdata.
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// USER_W : Width for i_chdr_tuser and o_chdr_tuser.
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// PIPELINE : Indicates whether to add pipeline stages to the input and/or
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// output. This can be: "NONE", "IN", "OUT", or "INOUT".
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//
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`default_nettype none
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module chdr_resize #(
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parameter I_CHDR_W = 64,
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parameter O_CHDR_W = 512,
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parameter I_DATA_W = I_CHDR_W,
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parameter O_DATA_W = O_CHDR_W,
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parameter USER_W = 1,
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parameter PIPELINE = "NONE"
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) (
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input wire clk,
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input wire rst,
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// Input
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input wire [I_DATA_W-1:0] i_chdr_tdata,
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input wire [ USER_W-1:0] i_chdr_tuser,
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input wire i_chdr_tlast,
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input wire i_chdr_tvalid,
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output wire i_chdr_tready,
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// Input
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output wire [O_DATA_W-1:0] o_chdr_tdata,
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output wire [ USER_W-1:0] o_chdr_tuser,
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output wire o_chdr_tlast,
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output wire o_chdr_tvalid,
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input wire o_chdr_tready
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);
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`define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
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// Determine the bus width of the CHDR converter, which is always the smaller
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// bus width of the input and output.
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localparam CONVERT_W = `MIN(I_DATA_W, O_DATA_W);
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// Determine if we need the bus down-sizer
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localparam DO_DOWNSIZE = (I_DATA_W > O_DATA_W);
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// Determine if we need the CHDR width converter
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localparam DO_CONVERT = (I_CHDR_W != O_CHDR_W);
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// Determine if we need the bus up-sizer
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localparam DO_UPSIZE = (I_DATA_W < O_DATA_W);
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// Determine the pipeline settings. We want pipeline stages on the input
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// and/or output, depending on the PIPELINE parameter, as well as between the
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// up-sizer and converter, and between the converter and down-sizer, any of
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// which may or may not be present. We don't, however, want back-to-back
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// pipeline stages (e.g., on the output of the down-sizer and the input to
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// the converter). If both an up/down-sizer and converter are used, the
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// settings below will turn on the adjacent pipeline stage in the converter
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// and turn off the corresponding pipeline stage in the up/down-sizer.
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localparam DOWNSIZE_PIPELINE =
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(PIPELINE == "IN" && DO_CONVERT) ? "IN" :
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(PIPELINE == "IN" && !DO_CONVERT) ? "IN" :
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(PIPELINE == "INOUT" && DO_CONVERT) ? "IN" :
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(PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
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(PIPELINE == "OUT" && DO_CONVERT) ? "NONE" :
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(PIPELINE == "OUT" && !DO_CONVERT) ? "OUT" :
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"NONE" ;
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localparam CONVERT_PIPELINE =
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(PIPELINE == "IN" && DO_DOWNSIZE) ? "IN" :
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(PIPELINE == "IN" && DO_UPSIZE ) ? "INOUT" :
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(PIPELINE == "IN" /* neither */) ? "IN" :
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(PIPELINE == "INOUT" && DO_DOWNSIZE) ? "INOUT" :
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(PIPELINE == "INOUT" && DO_UPSIZE ) ? "INOUT" :
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(PIPELINE == "INOUT" /* neither */) ? "INOUT" :
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(PIPELINE == "OUT" && DO_DOWNSIZE) ? "INOUT" :
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(PIPELINE == "OUT" && DO_UPSIZE ) ? "OUT" :
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(PIPELINE == "OUT" /* neither */) ? "OUT" :
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"NONE" ;
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localparam UPSIZE_PIPELINE =
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(PIPELINE == "IN" && DO_CONVERT) ? "NONE" :
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(PIPELINE == "IN" && !DO_CONVERT) ? "IN" :
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(PIPELINE == "INOUT" && DO_CONVERT) ? "OUT" :
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(PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
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(PIPELINE == "OUT" && DO_CONVERT) ? "OUT" :
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(PIPELINE == "OUT" && !DO_CONVERT) ? "OUT" :
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"NONE" ;
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generate
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//-------------------------------------------------------------------------
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// Check Parameters
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//-------------------------------------------------------------------------
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if (!(
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// All widths must be valid CHDR widths (at least 64 and powers of 2)
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(2**$clog2(I_CHDR_W) == I_CHDR_W) &&
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(2**$clog2(O_CHDR_W) == O_CHDR_W) &&
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(2**$clog2(I_DATA_W) == I_DATA_W) &&
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(2**$clog2(O_DATA_W) == O_DATA_W) &&
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(I_CHDR_W >= 64) &&
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(O_CHDR_W >= 64) &&
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(I_DATA_W >= 64) &&
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(O_DATA_W >= 64) &&
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// The converter width must match the smaller bus width. It doesn't work
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// on buses wider than the CHDR width.
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(CONVERT_W == `MIN(I_CHDR_W, O_CHDR_W))
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)) begin : gen_error
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ERROR__Invalid_CHDR_or_data_width_parameters();
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end
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//-------------------------------------------------------------------------
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// TUSER Data Path
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//-------------------------------------------------------------------------
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//
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// Sample TUSER at the beginning of the input packet and output it for the
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// duration of the output packet.
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//
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//-------------------------------------------------------------------------
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if (DO_DOWNSIZE || DO_UPSIZE || DO_CONVERT || PIPELINE == "INOUT") begin : gen_tuser_buffer
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if (!DO_DOWNSIZE && !DO_UPSIZE && DO_CONVERT && PIPELINE == "NONE") begin : gen_tuser_reg
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// In this case, there's a combinatorial path from i_chdr to o_chdr, so
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// we can't use a FIFO to buffer TUSER.
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// Track start of packet on o_chdr
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reg o_chdr_sop = 1;
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always @(posedge clk) begin
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if (rst) begin
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o_chdr_sop <= 1;
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end else if (o_chdr_tvalid && o_chdr_tready) begin
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o_chdr_sop <= o_chdr_tlast;
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end
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end
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reg [USER_W-1:0] o_tuser_reg;
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always @(posedge clk) begin
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if (rst) begin
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o_tuser_reg <= {USER_W{1'bX}};
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end else if (o_chdr_tvalid && o_chdr_tready && o_chdr_sop) begin
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o_tuser_reg <= i_chdr_tuser;
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end
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end
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// Pass through TUSER for first word in the packet, then use a holding
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// register for the rest of the packet.
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assign o_chdr_tuser = (o_chdr_sop) ? i_chdr_tuser : o_tuser_reg;
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end else begin : gen_tuser_fifo
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// In this case we use a FIFO to buffer TUSER.
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// Track start of packet on i_chdr
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reg i_chdr_sop = 1;
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always @(posedge clk) begin
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if (rst) begin
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i_chdr_sop <= 1;
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end else if (i_chdr_tvalid && i_chdr_tready) begin
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i_chdr_sop <= i_chdr_tlast;
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end
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end
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axi_fifo_short #(
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.WIDTH (USER_W)
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) axi_fifo_short_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata (i_chdr_tuser),
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.i_tvalid (i_chdr_tvalid && i_chdr_tready && i_chdr_sop),
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.i_tready (),
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.o_tdata (o_chdr_tuser),
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.o_tvalid (),
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.o_tready (o_chdr_tready && o_chdr_tvalid && o_chdr_tlast),
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.space (),
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.occupied ()
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);
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end
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end else begin : gen_tuser_pass_through
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// In this case there's no logic on the data path, so we can pass TUSER
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// through directly.
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assign o_chdr_tuser = i_chdr_tuser;
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end
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//-------------------------------------------------------------------------
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// Down-Size Input Bus Width
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//-------------------------------------------------------------------------
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wire [CONVERT_W-1:0] resized_tdata;
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wire resized_tlast;
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wire resized_tvalid;
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wire resized_tready;
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if (DO_DOWNSIZE) begin : gen_bus_downsize
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axis_width_conv #(
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.WORD_W (CONVERT_W),
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.IN_WORDS (I_DATA_W / CONVERT_W),
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.OUT_WORDS (1),
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.SYNC_CLKS (1),
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.PIPELINE (DOWNSIZE_PIPELINE)
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) axis_width_conv_i (
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.s_axis_aclk (clk),
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.s_axis_rst (rst),
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.s_axis_tdata (i_chdr_tdata),
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.s_axis_tkeep ({(I_DATA_W / CONVERT_W){1'b1}}),
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.s_axis_tlast (i_chdr_tlast),
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.s_axis_tvalid (i_chdr_tvalid),
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.s_axis_tready (i_chdr_tready),
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.m_axis_aclk (clk),
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.m_axis_rst (rst),
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.m_axis_tdata (resized_tdata),
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.m_axis_tkeep (),
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.m_axis_tlast (resized_tlast),
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.m_axis_tvalid (resized_tvalid),
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.m_axis_tready (resized_tready)
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);
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end else begin : gen_no_bus_downsize
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assign resized_tdata = i_chdr_tdata;
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assign resized_tlast = i_chdr_tlast;
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assign resized_tvalid = i_chdr_tvalid;
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assign i_chdr_tready = resized_tready;
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end
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//-------------------------------------------------------------------------
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// CHDR Width Protocol Conversion
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//-------------------------------------------------------------------------
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wire [CONVERT_W-1:0] converted_tdata;
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wire converted_tlast;
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wire converted_tvalid;
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wire converted_tready;
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if (DO_CONVERT) begin : gen_convert
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if (I_CHDR_W > O_CHDR_W) begin : gen_chdr_convert_down
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chdr_convert_down #(
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.I_CHDR_W (I_CHDR_W),
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.DATA_W (CONVERT_W),
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.PIPELINE (CONVERT_PIPELINE)
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) chdr_convert_down_i (
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.clk (clk),
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.rst (rst),
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.i_chdr_tdata (resized_tdata),
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.i_chdr_tlast (resized_tlast),
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.i_chdr_tvalid (resized_tvalid),
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.i_chdr_tready (resized_tready),
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.o_chdr_tdata (o_chdr_tdata),
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.o_chdr_tlast (o_chdr_tlast),
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.o_chdr_tvalid (o_chdr_tvalid),
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.o_chdr_tready (o_chdr_tready)
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);
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end else if (I_CHDR_W < O_CHDR_W) begin : gen_chdr_convert_up
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chdr_convert_up #(
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.DATA_W (CONVERT_W),
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.O_CHDR_W (O_CHDR_W),
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.PIPELINE (PIPELINE)
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) chdr_convert_up_i (
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.clk (clk),
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.rst (rst),
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.i_chdr_tdata (resized_tdata),
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.i_chdr_tlast (resized_tlast),
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.i_chdr_tvalid (resized_tvalid),
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.i_chdr_tready (resized_tready),
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.o_chdr_tdata (converted_tdata),
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.o_chdr_tlast (converted_tlast),
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.o_chdr_tvalid (converted_tvalid),
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.o_chdr_tready (converted_tready)
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);
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end
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end else begin : gen_no_convert
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if (PIPELINE == "INOUT" && !DO_DOWNSIZE && !DO_UPSIZE) begin : gen_pipeline
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// In this case there's no conversion or up-size/down-size, so we're
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// just passing the data through unchanged. However, if PIPELINE is set
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// to INOUT then we should have a pipeline stage, so we add that here.
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axi_fifo_flop2 #(
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.WIDTH (1 + CONVERT_W)
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) axi_fifo_flop2_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata ({ resized_tlast, resized_tdata }),
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.i_tvalid (resized_tvalid),
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.i_tready (resized_tready),
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.o_tdata ({ converted_tlast, converted_tdata }),
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.o_tvalid (converted_tvalid),
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.o_tready (converted_tready),
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.space (),
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.occupied ()
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);
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end else begin : gen_convert_bypass
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assign converted_tdata = resized_tdata;
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assign converted_tlast = resized_tlast;
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assign converted_tvalid = resized_tvalid;
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assign resized_tready = converted_tready;
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end
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end
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//-------------------------------------------------------------------------
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// Up-Size Output Bus Width
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//-------------------------------------------------------------------------
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if (DO_UPSIZE) begin : gen_bus_upsize
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axis_width_conv #(
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.WORD_W (CONVERT_W),
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.IN_WORDS (1),
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.OUT_WORDS (O_DATA_W / CONVERT_W),
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.SYNC_CLKS (1),
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.PIPELINE (UPSIZE_PIPELINE)
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) axis_width_conv_i (
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.s_axis_aclk (clk),
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.s_axis_rst (rst),
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.s_axis_tdata (converted_tdata),
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.s_axis_tkeep (1'b1),
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.s_axis_tlast (converted_tlast),
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.s_axis_tvalid (converted_tvalid),
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.s_axis_tready (converted_tready),
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.m_axis_aclk (clk),
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.m_axis_rst (rst),
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.m_axis_tdata (o_chdr_tdata),
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.m_axis_tkeep (),
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.m_axis_tlast (o_chdr_tlast),
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.m_axis_tvalid (o_chdr_tvalid),
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.m_axis_tready (o_chdr_tready)
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);
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end else begin : gen_no_bus_upsize
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assign o_chdr_tdata = converted_tdata;
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assign o_chdr_tlast = converted_tlast;
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assign o_chdr_tvalid = converted_tvalid;
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assign converted_tready = o_chdr_tready;
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end
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endgenerate
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endmodule
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`default_nettype wire
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