Wade Fife
81bb2ae28f
This adds the ability to do IP generation and FPGA builds using the --jobs (-j) option with Make. For example, rather than generating each IP one after another, you can generate up to N at a time using N Vivado instances. This greatly reduces the IP generation time. Similarly, parallel jobs can be used to easily build different FPGA variants simultaneously. Because FPGA builds can consume a lot of memory, care must be taken to ensure that the number of jobs is not too high for the amount of memory available. New IP make targets were added for each USRP so that IP can be built separately from the FPGA. The IP targets are now a dependency on each FPGA target. For example, you can generate the IP for X310 using 4 parallel jobs using the following command: make -j4 X310_IP Or, build two X310 bitstreams simultaneously: make -j2 X310_XG X310_HG Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
24 lines
787 B
Makefile
24 lines
787 B
Makefile
#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Add C/C++/tcl files relative to usrp3/lib/hls/<ip> directory
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HLS_IP_ADDSUB_HLS_LIB_SRCS = $(addprefix $(HLS_IP_DIR)/addsub_hls/, \
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addsub_hls.cpp \
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addsub_hls.tcl \
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)
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# HLS output artifact points to the ip/hdl/verilog folder. The build process
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# will glob all the files in this directory, including *.dat files.
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HLS_IP_ADDSUB_HLS_OUTS = $(IP_BUILD_DIR)/addsub_hls/solution/impl/ip/hdl/verilog
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.INTERMEDIATE: HLS_IP_ADDSUB_HLS_TRGT
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$(HLS_IP_ADDSUB_HLS_OUTS): HLS_IP_ADDSUB_HLS_TRGT
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@:
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# Build with HLS
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HLS_IP_ADDSUB_HLS_TRGT: $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
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$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
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