131 lines
5.1 KiB
Verilog
131 lines
5.1 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_splitter
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//
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// Description:
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//
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// This block splits a single control port interface into multiple. It is used
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// when you have a single master that needs to access multiple slaves. For
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// example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// Note that this block does not do any address decoding, so the connected
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// slaves must use non-overlapping address spaces.
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//
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// This module takes the request received by its single slave interface and
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// outputs it on all its master interfaces. In the opposite direction, it takes
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// the responses received by its multiple master interfaces and combines them
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// into a single response on its slave interface. This is done by using the ack
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// bit of each response to mask the other bits of the response, then OR'ing all
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// of the masked responses together onto a single response bus. This is valid
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// because only one block is allowed to respond to a single request.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves you want to connect to a master.
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//
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module ctrlport_splitter #(
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parameter NUM_SLAVES = 2
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Slave Interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// Master Interfaces
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output wire [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
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output wire [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
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output wire [20*NUM_SLAVES-1:0] m_ctrlport_req_addr,
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output wire [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
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output wire [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
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output wire [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
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output wire [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
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input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
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);
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generate
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if (NUM_SLAVES == 1) begin : gen_no_split
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// No logic is needed if only one slave is going to be connected
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assign m_ctrlport_req_wr = s_ctrlport_req_wr;
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assign m_ctrlport_req_rd = s_ctrlport_req_rd;
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assign m_ctrlport_req_addr = s_ctrlport_req_addr;
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assign m_ctrlport_req_data = s_ctrlport_req_data;
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assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
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assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
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assign m_ctrlport_req_time = s_ctrlport_req_time;
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always @(*) begin
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s_ctrlport_resp_ack = m_ctrlport_resp_ack;
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s_ctrlport_resp_status = m_ctrlport_resp_status;
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s_ctrlport_resp_data = m_ctrlport_resp_data;
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end
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end else begin : gen_splitter
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//---------------------------------------------------------------------------
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// Split the requests among the slaves
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//---------------------------------------------------------------------------
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genvar i;
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for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
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// No special logic is required to split the requests from the master among
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// multiple slaves.
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assign m_ctrlport_req_wr[i] = s_ctrlport_req_wr;
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assign m_ctrlport_req_rd[i] = s_ctrlport_req_rd;
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assign m_ctrlport_req_addr[20*i+:20] = s_ctrlport_req_addr;
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assign m_ctrlport_req_data[32*i+:32] = s_ctrlport_req_data;
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assign m_ctrlport_req_byte_en[4*i+:4] = s_ctrlport_req_byte_en;
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assign m_ctrlport_req_has_time[i] = s_ctrlport_req_has_time;
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assign m_ctrlport_req_time[64*i+:64] = s_ctrlport_req_time;
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end
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//---------------------------------------------------------------------------
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// Decode the responses
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//---------------------------------------------------------------------------
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reg [31:0] data;
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reg [ 1:0] status;
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reg ack = 0;
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// Take the responses and mask them with ack, then OR them together
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always @(*) begin : comb_decode
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integer s;
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data = 0;
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status = 0;
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ack = 0;
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for (s = 0; s < NUM_SLAVES; s = s+1) begin
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data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
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status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
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ack = ack | m_ctrlport_resp_ack[s];
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end
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end
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// Register the output to break combinatorial path
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always @(posedge ctrlport_clk) begin : response_reg
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 0;
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end else begin
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s_ctrlport_resp_data <= data;
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s_ctrlport_resp_status <= status;
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s_ctrlport_resp_ack <= ack;
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end
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end
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end
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endgenerate
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endmodule
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