181 lines
5.7 KiB
Verilog
181 lines
5.7 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: gearbox_2x1
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//
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// Description:
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//
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// Moves data between two clock domains at a constant data rate. This module
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// requires that the clocks be related and that there is a 2:1 ratio between
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// the two clocks. Static timing analysis is assumed for the clock domain
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// crossing. The module supports going from a slow clock to a fast clock (2
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// words per 1x clock cycle to 1 word per 2x clock cycle) or from a fast
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// clock to a slow clock (1 word per 1x clock cycle to 2 words per 2x clock
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// cycles) depending on the parameters provided.
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//
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// Note that there are no tready signals, so downstream logic must always be
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// ready.
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//
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// Parameters:
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//
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// WORD_W : Bits per word
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// IN_WORDS : Number of input words per clock cycle
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// OUT_WORDS : Number of output words per clock cycle
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// BIG_ENDIAN : Order in which to input/output words when multiple words per
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// clock cycle are needed. Little endian means the first word is
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// in the least-significant position. Big endian means the first
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// word is in the most-significant position.
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//
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module gearbox_2x1 #(
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parameter WORD_W = 8,
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parameter IN_WORDS = 2,
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parameter OUT_WORDS = 1,
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parameter BIG_ENDIAN = 0
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) (
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input wire i_clk,
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input wire i_rst,
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input wire [IN_WORDS*WORD_W-1:0] i_tdata,
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input wire i_tvalid,
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input wire o_clk,
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input wire o_rst,
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output reg [OUT_WORDS*WORD_W-1:0] o_tdata,
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output reg o_tvalid = 1'b0
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);
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localparam IN_W = WORD_W * IN_WORDS;
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localparam OUT_W = WORD_W * OUT_WORDS;
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generate
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// Make sure the ratios are supported
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if (IN_WORDS != 2*OUT_WORDS && OUT_WORDS != 2*IN_WORDS) begin : gen_ERROR
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IN_WORDS_and_OUT_WORDS_must_have_a_2_to_1_ratio();
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end
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//-------------------------------------------------------------------------
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// 2 words to 1 word (slow clock to fast clock)
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//-------------------------------------------------------------------------
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if (IN_WORDS > OUT_WORDS) begin : gen_slow_to_fast
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reg [IN_W-1:0] i_tdata_reg;
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reg i_tvalid_reg;
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reg i_toggle = 1'b0;
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always @(posedge i_clk) begin
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if (i_rst) begin
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i_tdata_reg <= 'bX;
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i_tvalid_reg <= 1'b0;
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i_toggle <= 1'b0;
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end else begin
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i_tdata_reg <= i_tdata;
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i_tvalid_reg <= i_tvalid;
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if (i_tvalid) begin
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i_toggle <= ~i_toggle;
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end
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end
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end
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reg [IN_W-1:0] o_tdata_reg;
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reg o_tvalid_reg = 1'b0;
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reg o_toggle;
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reg o_toggle_dly;
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reg o_data_sel;
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always @(posedge o_clk) begin
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if (o_rst) begin
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o_tdata_reg <= 'bX;
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o_tvalid <= 1'b0;
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o_tvalid_reg <= 1'b0;
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o_toggle <= 1'bX;
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o_toggle_dly <= 1'bX;
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o_data_sel <= 1'bX;
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end else begin
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// Clock crossing
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o_tvalid_reg <= i_tvalid_reg;
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o_toggle <= i_toggle;
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o_tdata_reg <= i_tdata_reg;
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// Determine which output to select
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o_toggle_dly <= o_toggle;
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o_data_sel <= BIG_ENDIAN ^ (o_toggle == o_toggle_dly);
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// Select the correct output for this clock cycle
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o_tvalid <= o_tvalid_reg;
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o_tdata <= o_data_sel ?
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o_tdata_reg[0 +: OUT_W] : o_tdata_reg[IN_W/2 +: OUT_W];
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end
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end
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//-------------------------------------------------------------------------
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// 1 word to 2 words (fast clock to slow clock)
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//-------------------------------------------------------------------------
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end else begin : gen_fast_to_slow
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reg [IN_W-1:0] i_gear_reg;
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reg [OUT_W-1:0] i_gear_tdata;
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reg i_gear_one_word = 1'b0;
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reg i_gear_tvalid = 1'b0;
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reg i_gear_tvalid_dly = 1'b0;
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always @(posedge i_clk) begin
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if (i_rst) begin
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i_gear_reg <= 'bX;
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i_gear_tdata <= 'bX;
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i_gear_one_word <= 1'b0;
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i_gear_tvalid <= 1'b0;
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i_gear_tvalid_dly <= 1'b0;
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end else begin
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// Default assignments
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i_gear_tvalid <= 1'b0;
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i_gear_tvalid_dly <= i_gear_tvalid;
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if (i_tvalid) begin
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// Track if the gearbox has one word saved
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i_gear_one_word <= ~i_gear_one_word;
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i_gear_reg <= i_tdata;
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if (i_gear_one_word) begin
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// This is the second word, so output the new word on i_gear_reg_t*
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i_gear_tdata <= BIG_ENDIAN ?
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{ i_gear_reg, i_tdata } : { i_tdata, i_gear_reg };
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i_gear_tvalid <= 1'b1;
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end
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end
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end
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end
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reg [OUT_W-1:0] o_gear_tdata;
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reg o_gear_tvalid = 1'b0;
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reg o_gear_tvalid_dly = 1'b0;
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reg o_tvalid_reg = 1'b0;
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always @(posedge o_clk) begin
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if (o_rst) begin
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o_gear_tvalid <= 1'b0;
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o_gear_tvalid_dly <= 1'b0;
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o_gear_tdata <= 'bX;
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o_tvalid <= 1'b0;
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o_tdata <= 'bX;
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end else begin
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// Clock crossing
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o_gear_tvalid <= i_gear_tvalid;
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o_gear_tvalid_dly <= i_gear_tvalid_dly;
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o_gear_tdata <= i_gear_tdata;
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// Control tvalid
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o_tvalid <= o_gear_tvalid | o_gear_tvalid_dly;
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o_tdata <= o_gear_tdata;
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end
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end
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end
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endgenerate
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endmodule
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