544 lines
20 KiB
Verilog
544 lines
20 KiB
Verilog
//
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// Copyright 2018 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: n3xx_mgt_wrapper
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//
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// Description:
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//
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// Wrapper for single MGT, including support for Aurora, WhiteRabbit, 10 GbE,
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// and 1 GbE.
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//
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// Parameters:
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//
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// PROTOCOL : Must be "10GbE", "1GbE", "Aurora", or "Disabled".
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// REG_DWIDTH : Data width of the AXI-Lite interface and RegPort
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// REG_AWIDTH : Address width of the AXI-Lite interface and RegPort\
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// GT_COMMON : Use GT Common ports on MGT
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// PORTNUM : Port number
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// MDIO_EN : Enables internal MDIO master
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// MDIO_PHYADDR : Address to use for the MDIO
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// BYTE_MTU : Log base 2 of the MTU size in bytes
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// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
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// adapters.
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// NODE_INST : RFNoC transport adapter node instance for this port
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// EN_RX_KV_MAP_CFG : Enable KV-map configuration port on transport adapter
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// EN_RX_RAW_PYLD : Enable raw UDP support on transport adapter
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//
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`default_nettype none
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module n3xx_mgt_wrapper #(
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parameter PROTOCOL = "10GbE",
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parameter REG_DWIDTH = 32,
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parameter REG_AWIDTH = 14,
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parameter REG_BASE = 16'h0000,
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parameter GT_COMMON = 1,
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parameter [ 7:0] PORTNUM = 8'd0,
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parameter MDIO_EN = 0,
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parameter [ 4:0] MDIO_PHYADDR = 5'd0,
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parameter BYTE_MTU = $clog2(8192),
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter NODE_INST = 0,
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parameter EN_RX_KV_MAP_CFG = 1,
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parameter EN_RX_RAW_PYLD = 1
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) (
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// Resets
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input wire areset,
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input wire bus_rst,
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// Clocks
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input wire gt_refclk,
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input wire gb_refclk,
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input wire misc_clk,
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input wire bus_clk,
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input wire user_clk,
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input wire sync_clk,
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// RegPort interface
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input wire reg_wr_req,
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input wire [REG_AWIDTH-1:0] reg_wr_addr,
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input wire [REG_DWIDTH-1:0] reg_wr_data,
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input wire reg_rd_req,
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input wire [REG_AWIDTH-1:0] reg_rd_addr,
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output wire reg_rd_resp,
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output wire [REG_DWIDTH-1:0] reg_rd_data,
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// High-speed IO
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output wire txp,
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output wire txn,
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input wire rxp,
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input wire rxn,
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// SFP low-speed IO
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input wire mod_present_n,
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input wire mod_rxlos,
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input wire mod_tx_fault,
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output wire mod_tx_disable,
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// GT Common
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input wire qpllrefclklost,
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input wire qplllock,
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input wire qplloutclk,
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input wire qplloutrefclk,
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output wire qpllreset,
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// Aurora MMCM
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input wire mmcm_locked,
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output wire gt_pll_lock,
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output wire gt_tx_out_clk_unbuf,
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// Vita router interface
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output wire [63:0] e2v_tdata,
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output wire e2v_tlast,
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output wire e2v_tvalid,
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input wire e2v_tready,
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input wire [63:0] v2e_tdata,
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input wire v2e_tlast,
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input wire v2e_tvalid,
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output wire v2e_tready,
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// CPU
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output wire [63:0] e2c_tdata,
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output wire [7:0] e2c_tkeep,
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output wire e2c_tlast,
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output wire e2c_tvalid,
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input wire e2c_tready,
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input wire [63:0] c2e_tdata,
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input wire [7:0] c2e_tkeep,
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input wire c2e_tlast,
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input wire c2e_tvalid,
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output wire c2e_tready,
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// MISC
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output wire [31:0] port_info,
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input wire [15:0] device_id,
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// Timebase Outputs
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output wire mod_pps,
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output wire mod_refclk,
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// Sideband White Rabbit Control
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input wire wr_reset_n,
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input wire wr_refclk,
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output wire wr_dac_sclk,
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output wire wr_dac_din,
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output wire wr_dac_clr_n,
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output wire wr_dac_cs_n,
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output wire wr_dac_ldac_n,
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output wire wr_eeprom_scl_o,
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input wire wr_eeprom_scl_i,
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output wire wr_eeprom_sda_o,
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input wire wr_eeprom_sda_i,
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input wire wr_uart_rx,
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output wire wr_uart_tx,
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// WR AXI Control
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output wire wr_axi_aclk,
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input wire wr_axi_aresetn,
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input wire [31:0] wr_axi_awaddr,
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input wire wr_axi_awvalid,
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output wire wr_axi_awready,
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input wire [REG_DWIDTH-1:0] wr_axi_wdata,
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input wire [REG_DWIDTH/8-1:0] wr_axi_wstrb,
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input wire wr_axi_wvalid,
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output wire wr_axi_wready,
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output wire [1:0] wr_axi_bresp,
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output wire wr_axi_bvalid,
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input wire wr_axi_bready,
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input wire [31:0] wr_axi_araddr,
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input wire wr_axi_arvalid,
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output wire wr_axi_arready,
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output wire [REG_DWIDTH-1:0] wr_axi_rdata,
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output wire [1:0] wr_axi_rresp,
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output wire wr_axi_rvalid,
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input wire wr_axi_rready,
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output wire wr_axi_rlast,
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output wire link_up,
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output wire activity
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);
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localparam [REG_AWIDTH-1:0] REG_BASE_MGT_IO = {REG_AWIDTH{1'b0}} + REG_BASE;
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localparam [REG_AWIDTH-1:0] REG_BASE_ETH_SWITCH = {REG_AWIDTH{1'b0}} + 16'h1000 + REG_BASE;
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// AXI4-Lite to RegPort (PS to PL Register Access)
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wire reg_rd_resp_io, reg_rd_resp_eth_if;
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wire [REG_DWIDTH-1:0] reg_rd_data_io, reg_rd_data_eth_if;
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// Regport Mux for response
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regport_resp_mux #(
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.WIDTH (REG_DWIDTH),
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.NUM_SLAVES (2)
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) reg_resp_mux_i (
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}),
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.sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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wire [63:0] mgto_tdata, mgti_tdata;
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wire [3:0] mgto_tuser, mgti_tuser;
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wire mgto_tlast, mgti_tlast, mgto_tvalid, mgti_tvalid, mgto_tready, mgti_tready;
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generate
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if (PROTOCOL != "WhiteRabbit") begin
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n3xx_mgt_io_core #(
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.PROTOCOL (PROTOCOL),
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.REG_BASE (REG_BASE_MGT_IO),
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.REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.REG_AWIDTH (REG_AWIDTH), // Width of the address bus
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.GT_COMMON (GT_COMMON),
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.MDIO_EN (MDIO_EN),
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.MDIO_PHYADDR (MDIO_PHYADDR),
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.PORTNUM (PORTNUM)
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) mgt_io_i (
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//must reset all channels on quad when other gtx core is reset
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.areset (areset),
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.gt_refclk (gt_refclk),
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.gb_refclk (gb_refclk),
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.misc_clk (misc_clk),
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.user_clk (user_clk),
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.sync_clk (sync_clk),
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.gt_tx_out_clk_unbuf(gt_tx_out_clk_unbuf),
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.bus_rst (bus_rst),
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.bus_clk (bus_clk),
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.qpllreset (qpllreset),
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.qplllock (qplllock),
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.qplloutclk (qplloutclk),
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.qplloutrefclk (qplloutrefclk),
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.qpllrefclklost (qpllrefclklost),
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.mmcm_locked (mmcm_locked),
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.gt_pll_lock (gt_pll_lock),
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.txp (txp),
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.txn (txn),
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.rxp (rxp),
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.rxn (rxn),
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.sfpp_rxlos (mod_rxlos),
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.sfpp_tx_fault (mod_tx_fault),
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.sfpp_tx_disable(mod_tx_disable),
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//RegPort
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_io),
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.reg_rd_data (reg_rd_data_io),
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// Vita to Ethernet
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.s_axis_tdata (mgti_tdata),
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.s_axis_tuser (mgti_tuser),
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.s_axis_tlast (mgti_tlast),
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.s_axis_tvalid (mgti_tvalid),
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.s_axis_tready (mgti_tready),
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// Ethernet to Vita
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.m_axis_tdata (mgto_tdata),
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.m_axis_tuser (mgto_tuser),
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.m_axis_tlast (mgto_tlast),
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.m_axis_tvalid (mgto_tvalid),
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.m_axis_tready (mgto_tready),
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.port_info (port_info),
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.link_up (link_up),
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.activity (activity)
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);
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end else begin
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//---------------------------------------------------------------------------------
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// White Rabbit
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//---------------------------------------------------------------------------------
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wire wr_sfp_scl, wr_sfp_sda_o, wr_sfp_sda_i;
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n3xx_wr_top #(
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.g_simulation(1'b0), // in std_logic
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.g_dpram_size(131072/4),
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.g_dpram_initf("../../../../bin/wrpc/wrc_phy16.bram")
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) wr_inst (
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.areset_n_i (wr_reset_n), // in std_logic; -- active low reset, optional
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.wr_refclk_buf_i (wr_refclk), // in std_logic; -- 20MHz VCXO after IBUFGDS
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.gige_refclk_buf_i (gt_refclk), // in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2
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.dac_sclk_o (wr_dac_sclk), // out std_logic; -- N3xx cWB-DAC-SCLK
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.dac_din_o (wr_dac_din), // out std_logic; -- N3xx cWB-DAC-DIN
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.dac_clr_n_o (wr_dac_clr_n), // out std_logic; -- N3xx cWB-DAC-nCLR
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.dac_cs_n_o (wr_dac_cs_n), // out std_logic; -- N3xx cWB-DAC-nSYNC
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.dac_ldac_n_o (wr_dac_ldac_n), // out std_logic; -- N3xx cWB-DAC-nLDAC
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.LED_ACT (activity), // out std_logic; -- connect to SFP+ ACT
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.LED_LINK (link_up), // out std_logic; -- connect to SFP+ LINK
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.sfp_txp_o (txp), // out std_logic;
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.sfp_txn_o (txn), // out std_logic;
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.sfp_rxp_i (rxp), // in std_logic;
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.sfp_rxn_i (rxn), // in std_logic;
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.sfp_mod_def0_b (mod_present_n), // in std_logic; - sfp detect
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.eeprom_scl_o (wr_eeprom_scl_o),
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.eeprom_scl_i (wr_eeprom_scl_i),
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.eeprom_sda_o (wr_eeprom_sda_o),
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.eeprom_sda_i (wr_eeprom_sda_i),
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.sfp_scl_o (wr_sfp_scl),
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.sfp_scl_i (wr_sfp_scl),
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.sfp_sda_o (wr_sfp_sda_o),
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.sfp_sda_i (wr_sfp_sda_i),
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.sfp_tx_fault_i (mod_tx_fault), // in std_logic;
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.sfp_tx_disable_o (mod_tx_disable), // out std_logic;
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.sfp_los_i (mod_rxlos), // in std_logic;
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.wr_uart_rxd (wr_uart_rx), // in std_logic;
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.wr_uart_txd (wr_uart_tx), // out std_logic;
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.s00_axi_aclk_o (wr_axi_aclk),
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.s00_axi_aresetn (wr_axi_aresetn),
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.s00_axi_awaddr (wr_axi_awaddr),
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.s00_axi_awprot (3'b0),
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.s00_axi_awvalid (wr_axi_awvalid),
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.s00_axi_awready (wr_axi_awready),
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.s00_axi_wdata (wr_axi_wdata),
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.s00_axi_wstrb (wr_axi_wstrb),
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.s00_axi_wvalid (wr_axi_wvalid),
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.s00_axi_wready (wr_axi_wready),
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.s00_axi_bresp (wr_axi_bresp),
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.s00_axi_bvalid (wr_axi_bvalid),
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.s00_axi_bready (wr_axi_bready),
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.s00_axi_araddr (wr_axi_araddr),
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.s00_axi_arprot (3'b0),
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.s00_axi_arvalid (wr_axi_arvalid),
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.s00_axi_arready (wr_axi_arready),
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.s00_axi_rdata (wr_axi_rdata),
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.s00_axi_rresp (wr_axi_rresp),
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.s00_axi_rvalid (wr_axi_rvalid),
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.s00_axi_rready (wr_axi_rready),
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.s00_axi_rlast (wr_axi_rlast),
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.axi_int_o (),
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.pps_o (mod_pps), // out std_logic;
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.clk_pps_o (mod_refclk), // out std_logic;
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.link_ok_o (), // out std_logic;
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.clk_sys_locked_o (), // out std_logic;
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.clk_dmtd_locked_o (), // out std_logic);
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.wr_debug0_o (),
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.wr_debug1_o ()
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);
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// TEMPORARY mimic the AXGE SFP EEROM
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sfp_eeprom sfp_eeprom_i (
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.clk_i(bus_clk),
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.sfp_scl(wr_sfp_scl),
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.sfp_sda_i(wr_sfp_sda_o),
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.sfp_sda_o(wr_sfp_sda_i));
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// Assign the port_info vector similarly to mgt_io_core
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localparam [7:0] COMPAT_NUM = 8'd2;
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localparam [7:0] MGT_PROTOCOL = 8'd4;
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assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM};
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// Tie off unused outputs.
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assign gt_pll_lock = 1'b0;
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assign gt_tx_out_clk_unbuf = 1'b0;
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end
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endgenerate
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generate
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// Tie off the Ethernet switch for these protocols that do not use it.
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if(PROTOCOL == "Aurora" || PROTOCOL == "Disabled") begin
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// Set unused wires to default values
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assign e2c_tdata = 64'h0;
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assign e2c_tkeep = 8'h0;
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assign e2c_tlast = 1'b0;
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assign e2c_tvalid = 1'b0;
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assign c2e_tready = 1'b1;
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assign reg_rd_resp_eth_if = 1'b0;
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assign reg_rd_data_eth_if = 'h0;
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assign e2v_tdata = mgto_tdata;
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assign e2v_tlast = mgto_tlast;
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assign e2v_tvalid = mgto_tvalid;
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assign mgto_tready = e2v_tready;
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assign mgti_tdata = v2e_tdata;
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assign mgti_tlast = v2e_tlast;
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assign mgti_tvalid = v2e_tvalid;
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assign v2e_tready = mgti_tready;
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end else if(PROTOCOL == "WhiteRabbit") begin
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// Set unused wires to default values
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assign e2c_tdata = 64'h0;
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assign e2c_tkeep = 8'h0;
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assign e2c_tlast = 1'b0;
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assign e2c_tvalid = 1'b0;
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assign c2e_tready = 1'b1;
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assign reg_rd_resp_eth_if = 1'b0;
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assign reg_rd_data_eth_if = 'h0;
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assign e2v_tdata = 64'b0;
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assign e2v_tlast = 1'b0;
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assign e2v_tvalid = 1'b0;
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assign v2e_tready = 1'b1;
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end else begin
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wire [3:0] e2c_tuser;
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wire [3:0] c2e_tuser;
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// In AXI Stream, tkeep is the byte qualifier that indicates
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// whether the content of the associated byte
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// of TDATA is processed as part of the data stream.
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// tuser as used in eth_switch is the numbier of valid bytes
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// Converting tuser to tkeep for ingress packets
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assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111
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: (e2c_tuser[2:0] == 3'd0) ? 8'b1111_1111
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: (e2c_tuser[2:0] == 3'd1) ? 8'b0000_0001
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: (e2c_tuser[2:0] == 3'd2) ? 8'b0000_0011
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: (e2c_tuser[2:0] == 3'd3) ? 8'b0000_0111
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: (e2c_tuser[2:0] == 3'd4) ? 8'b0000_1111
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: (e2c_tuser[2:0] == 3'd5) ? 8'b0001_1111
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: (e2c_tuser[2:0] == 3'd6) ? 8'b0011_1111
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: 8'b0111_1111;
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// Converting tkeep to tuser for egress packets
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assign c2e_tuser = ~c2e_tlast ? 4'd0
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: (c2e_tkeep == 8'b1111_1111) ? 4'd0
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: (c2e_tkeep == 8'b0111_1111) ? 4'd7
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: (c2e_tkeep == 8'b0011_1111) ? 4'd6
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: (c2e_tkeep == 8'b0001_1111) ? 4'd5
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: (c2e_tkeep == 8'b0000_1111) ? 4'd4
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: (c2e_tkeep == 8'b0000_0111) ? 4'd3
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: (c2e_tkeep == 8'b0000_0011) ? 4'd2
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: (c2e_tkeep == 8'b0000_0001) ? 4'd1
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: 4'd0;
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if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_eth_ipv4_interface_wrapper
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eth_ipv4_interface_wrapper #(
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.PROTOVER (RFNOC_PROTOVER),
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.CPU_FIFO_SIZE (BYTE_MTU),
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.CHDR_FIFO_SIZE (BYTE_MTU),
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.NODE_INST (NODE_INST),
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.REG_AWIDTH (REG_AWIDTH),
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.BASE (REG_BASE_ETH_SWITCH),
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.SYNC (1),
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.EN_RX_KV_MAP_CFG (EN_RX_KV_MAP_CFG),
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.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD)
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) eth_ipv4_interface_wrapper_i (
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.bus_clk (bus_clk),
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.bus_rst (bus_rst),
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.device_id (device_id),
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|
.reg_wr_req (reg_wr_req),
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|
.reg_wr_addr (reg_wr_addr),
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|
.reg_wr_data (reg_wr_data),
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|
.reg_rd_req (reg_rd_req),
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|
.reg_rd_addr (reg_rd_addr),
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|
.reg_rd_resp (reg_rd_resp_eth_if),
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|
.reg_rd_data (reg_rd_data_eth_if),
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|
.my_mac (),
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|
.my_ip (),
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|
.my_udp_chdr_port (),
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|
.eth_clk (bus_clk),
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|
.eth_rst (bus_rst),
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|
.eth_pause_req (),
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|
.eth_tx_tdata (mgti_tdata),
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|
.eth_tx_tuser (mgti_tuser),
|
|
.eth_tx_tkeep (),
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|
.eth_tx_tlast (mgti_tlast),
|
|
.eth_tx_tvalid (mgti_tvalid),
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|
.eth_tx_tready (mgti_tready),
|
|
.eth_rx_tdata (mgto_tdata),
|
|
.eth_rx_tuser (mgto_tuser),
|
|
.eth_rx_tlast (mgto_tlast),
|
|
.eth_rx_tvalid (mgto_tvalid),
|
|
.eth_rx_tready (mgto_tready),
|
|
.e2v_tdata (e2v_tdata),
|
|
.e2v_tlast (e2v_tlast),
|
|
.e2v_tvalid (e2v_tvalid),
|
|
.e2v_tready (e2v_tready),
|
|
.v2e_tdata (v2e_tdata),
|
|
.v2e_tlast (v2e_tlast),
|
|
.v2e_tvalid (v2e_tvalid),
|
|
.v2e_tready (v2e_tready),
|
|
.cpu_clk (bus_clk),
|
|
.cpu_rst (bus_rst),
|
|
.e2c_tdata (e2c_tdata),
|
|
.e2c_tuser (e2c_tuser),
|
|
.e2c_tlast (e2c_tlast),
|
|
.e2c_tvalid (e2c_tvalid),
|
|
.e2c_tready (e2c_tready),
|
|
.c2e_tdata (c2e_tdata),
|
|
.c2e_tuser (c2e_tuser),
|
|
.c2e_tlast (c2e_tlast),
|
|
.c2e_tvalid (c2e_tvalid),
|
|
.c2e_tready (c2e_tready)
|
|
);
|
|
end // gen_eth_ipv4_interface_wrapper
|
|
else begin : gen_eth_interface
|
|
eth_interface #(
|
|
.PROTOVER (RFNOC_PROTOVER),
|
|
.MTU (BYTE_MTU-3), // Log base 2 of the MTU in 64-bit words
|
|
.NODE_INST (NODE_INST),
|
|
.REG_AWIDTH (REG_AWIDTH),
|
|
.BASE (REG_BASE_ETH_SWITCH)
|
|
) eth_interface (
|
|
.clk (bus_clk),
|
|
.reset (bus_rst),
|
|
.device_id (device_id),
|
|
.reg_wr_req (reg_wr_req),
|
|
.reg_wr_addr (reg_wr_addr),
|
|
.reg_wr_data (reg_wr_data),
|
|
.reg_rd_req (reg_rd_req),
|
|
.reg_rd_addr (reg_rd_addr),
|
|
.reg_rd_resp (reg_rd_resp_eth_if),
|
|
.reg_rd_data (reg_rd_data_eth_if),
|
|
.my_mac (),
|
|
.my_ip (),
|
|
.my_udp_port (),
|
|
.eth_tx_tdata (mgti_tdata),
|
|
.eth_tx_tuser (mgti_tuser),
|
|
.eth_tx_tlast (mgti_tlast),
|
|
.eth_tx_tvalid (mgti_tvalid),
|
|
.eth_tx_tready (mgti_tready),
|
|
.eth_rx_tdata (mgto_tdata),
|
|
.eth_rx_tuser (mgto_tuser),
|
|
.eth_rx_tlast (mgto_tlast),
|
|
.eth_rx_tvalid (mgto_tvalid),
|
|
.eth_rx_tready (mgto_tready),
|
|
.e2v_tdata (e2v_tdata),
|
|
.e2v_tlast (e2v_tlast),
|
|
.e2v_tvalid (e2v_tvalid),
|
|
.e2v_tready (e2v_tready),
|
|
.v2e_tdata (v2e_tdata),
|
|
.v2e_tlast (v2e_tlast),
|
|
.v2e_tvalid (v2e_tvalid),
|
|
.v2e_tready (v2e_tready),
|
|
.e2c_tdata (e2c_tdata),
|
|
.e2c_tuser (e2c_tuser),
|
|
.e2c_tlast (e2c_tlast),
|
|
.e2c_tvalid (e2c_tvalid),
|
|
.e2c_tready (e2c_tready),
|
|
.c2e_tdata (c2e_tdata),
|
|
.c2e_tuser (c2e_tuser),
|
|
.c2e_tlast (c2e_tlast),
|
|
.c2e_tvalid (c2e_tvalid),
|
|
.c2e_tready (c2e_tready)
|
|
);
|
|
end // gen_eth_interface
|
|
end
|
|
endgenerate
|
|
|
|
endmodule // n3xx_mgt_wrapper
|
|
|
|
|
|
`default_nettype wire
|