46 lines
1.4 KiB
Makefile
46 lines
1.4 KiB
Makefile
#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir.
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BASE_DIR = ../../../../top
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its
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# dependencies.
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_OOT_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = rfnoc_block_logpwr_all_tb glbl
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SIM_SRCS = \
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$(abspath rfnoc_block_logpwr_tb.sv) \
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$(abspath rfnoc_block_logpwr_all_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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