Files
b210-k7-fpga/lib/packet_proc/arm_deframer.v
T
+18 6b67702ad7 Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
2020-01-28 09:35:36 -08:00

120 lines
4.2 KiB
Verilog

/////////////////////////////////////////////////////////////////////
//
// Copyright 2017 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: arm_deframer
// Description:
// Adds 6 bytes of Zeros at the beginning of every packet. It aligns the
// 64-bit words of the ethernet packet to be used later for classifying the
// packets. The module is based on xge64_to_axi64 and has lesser
// functionality.
// Note that the block only works for padding 6 bytes.
//
/////////////////////////////////////////////////////////////////////
module arm_deframer (
// Clocks and Reset
input wire clk,
input wire reset,
input wire clear,
// Slave AXI Interface
input wire [63:0] s_axis_tdata,
input wire [3:0] s_axis_tuser, //used as tkeep here
input wire s_axis_tlast,
input wire s_axis_tvalid,
output reg s_axis_tready,
// Master AXI Interface
output reg [63:0] m_axis_tdata,
output reg [3:0] m_axis_tuser, //used as tkeep here
output reg m_axis_tlast,
output reg m_axis_tvalid,
input wire m_axis_tready
);
// State Machine States
localparam START = 2'b00;
localparam BODY = 2'b01;
localparam EXTRA = 2'b10;
localparam PAD_BYTES = 3'b110; //6 bytes
wire new_line;
wire valid_beat;
reg [1:0] state = 2'b00, next_state=2'b00;
reg [47:0] holding_reg;
reg [2:0] holding_user;
// New line will be created by padding 6 bytes if the valid bytes on the
// last line are greater than 2 bytes(3 to 7 bytes) or all 8 bytes are valid.
assign new_line = (s_axis_tuser[2:0] > 3'b010) || (s_axis_tuser[2:0] == 3'b000);
assign valid_beat = s_axis_tvalid & m_axis_tready;
always @(posedge clk) begin
if (reset | clear) begin
state <= START;
end else begin
state <=next_state;
end
end
// holding last 48 bits from input tdata on every valid_beat.
always @(posedge clk)begin
if (s_axis_tvalid & s_axis_tready) begin
// Register the last 6 bytes of data for one cycle
holding_reg <= s_axis_tdata[63:16];
// Register the tuser in case there is a new line
// tuser should be valid for one extra cycle in that case
holding_user <= s_axis_tuser[2:0];
end
end
// Outputs
always @(*) begin
m_axis_tdata = 64'b0;
m_axis_tvalid = 1'b0;
m_axis_tlast = 1'b0;
m_axis_tuser = 4'b0;
s_axis_tready = 1'b1;
case (state)
START : begin
// Pad with 6 bytes of Zeros at the beginning of the packet
// Shift the first 2 bytes to the end
m_axis_tdata = {s_axis_tdata[15:0], 48'b0};
m_axis_tvalid = s_axis_tvalid;
m_axis_tlast = s_axis_tlast;
m_axis_tuser = 4'b0;
s_axis_tready = m_axis_tready;
if(valid_beat) next_state = BODY;
else next_state = START;
end
BODY : begin
// Shift the remaining packet by 6 bytes.
// Here we're using register version of data and tvalid.
m_axis_tdata = {s_axis_tdata[15:0], holding_reg};
m_axis_tvalid = s_axis_tvalid;
m_axis_tlast = new_line? 1'b0: s_axis_tvalid & s_axis_tlast;
// Modify the tuser according to the new packet i.e. add 6 to it.
m_axis_tuser = (new_line & s_axis_tlast) ? 4'b0: {1'b0, s_axis_tuser[2:0] + PAD_BYTES};
s_axis_tready = m_axis_tready;
if (valid_beat & s_axis_tlast) next_state = new_line ? EXTRA : START;
else next_state = BODY;
end
EXTRA : begin
m_axis_tdata = {16'b0, holding_reg};
m_axis_tvalid = 1'b1;
m_axis_tlast = 1'b1;
// Modify the tuser according to the new shifted packet i.e. add 6 to it.
m_axis_tuser = {1'b0, holding_user + PAD_BYTES};
// We need to hold off any comming upstream data i.e not ready until
// downstream done consuming this data
s_axis_tready = 1'b0;
if (m_axis_tready) next_state = START;
else next_state = EXTRA;
end
default : begin
m_axis_tdata = 64'b0;
m_axis_tvalid = 1'b0;
m_axis_tlast = 1'b0;
m_axis_tuser = 4'b0;
s_axis_tready = 1'b1;
next_state = START;
end
endcase
end
endmodule // arm_deframer