140 lines
3.1 KiB
Verilog
140 lines
3.1 KiB
Verilog
//
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// Test Virtual FIFO's by streaming modulo 2^32 counter (replicated in upper
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// and lower 32bits). Test result by tracking count on receive and using
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// sticky flag for error indication.
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// Also provide signal from MSB of 32bit count to blink LED.
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//
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module axi_test_vfifo
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#(parameter PACKET_SIZE = 128)
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(
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input aclk,
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input aresetn,
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input enable,
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// AXI Stream Out
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output reg out_axis_tvalid,
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input out_axis_tready,
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output [63 : 0] out_axis_tdata,
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output reg [7 : 0] out_axis_tstrb,
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output reg [7 : 0] out_axis_tkeep,
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output reg out_axis_tlast,
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output reg [0 : 0] out_axis_tid,
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output reg [0 : 0] out_axis_tdest,
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input vfifo_full,
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// AXI Stream In
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input in_axis_tvalid,
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output reg in_axis_tready,
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input [63 : 0] in_axis_tdata,
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input [7 : 0] in_axis_tstrb,
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input [7 : 0] in_axis_tkeep,
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input in_axis_tlast,
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input [0 : 0] in_axis_tid,
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input [0 : 0] in_axis_tdest,
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// Flags
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output reg flag_error,
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output heartbeat_in,
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output heartbeat_out,
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output [31:0] expected_count
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);
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reg [31:0] out_count;
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reg [31:0] in_count;
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reg [63:0] in_axis_tdata_reg;
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reg in_data_valid;
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//
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// Output
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//
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always @(posedge aclk)
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if (!aresetn) begin
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out_count <= 0;
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out_axis_tvalid <= 0;
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out_axis_tid <= 0; // Don't care.
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out_axis_tdest <= 0; // Only use port 0 of VFIFO.
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out_axis_tstrb <= 0; // Unused in VFIFO
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out_axis_tkeep <= 8'hFF; // Always use every byte of data
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out_axis_tlast <= 1'b0;
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end else if (enable) begin
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if (~vfifo_full) begin
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// Always ready to output new count value.
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out_axis_tvalid <= 1;
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if (out_axis_tready)
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out_count <= out_count + 1;
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// Assert TLAST every PACKET_SIZE beats.
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if (out_count[15:0] == PACKET_SIZE)
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out_axis_tlast <= 1'b1;
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else
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out_axis_tlast <= 1'b0;
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end else begin
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out_axis_tvalid <= 0;
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end
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end else begin
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out_axis_tlast <= 1'b0;
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out_axis_tvalid <= 0;
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end
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assign out_axis_tdata = {out_count,out_count};
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assign heartbeat_out = out_count[28];
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//
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// Input (Ignore TLAST signal)
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//
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always @(posedge aclk)
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if (!aresetn) begin
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in_axis_tready <= 0;
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in_axis_tdata_reg <= 0;
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in_data_valid <= 0;
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end else if (enable) begin
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in_axis_tready <= 1;
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in_axis_tdata_reg <= in_axis_tdata;
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if (in_axis_tvalid)
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in_data_valid <= 1;
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else
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in_data_valid <= 0;
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end else begin
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in_data_valid <= 0;
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in_axis_tready <= 0;
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end // else: !if(enable)
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assign heartbeat_in = in_count[28];
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//
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// Input Checker
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//
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always @(posedge aclk)
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if (!aresetn) begin
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in_count <= 0;
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flag_error <= 0;
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end else if (enable) begin
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if (in_data_valid) begin
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if ((in_axis_tdata_reg[63:32] != in_count) || (in_axis_tdata_reg[31:0] != in_count))
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begin
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flag_error <= 1;
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in_count <= in_axis_tdata_reg[63:32] + 1;
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end
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else
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begin
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flag_error <= 0;
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in_count <= in_count + 1;
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end
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end
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end
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assign expected_count = in_count;
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endmodule // axi_test_vfifo
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