602 lines
22 KiB
Verilog
602 lines
22 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_dio
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//
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// Description:
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//
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// This module contains the motherboard registers for the DIO
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// auxiliary board and the logic to drive these GPIO signals.
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// Arbitration between different sources to control the state
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// of the GPIO lines includes support for the following sources:
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// - s_ctrlport_* (combination of CtrlPort from PS AXI and radio blocks)
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// - PS dio control from Processing System's GPIOs
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// - ATR state (up to two DBs)
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// - User Application
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// - radio-controlled digital bus interface
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// For a visual representation of how the different sources are
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// arbitrated, as well as representation on what each source control
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// register refers to, please refer to the "Front-Panel Programmable
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// GPIOs" section of the USRP Manual.
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//
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// Parameters:
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//
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// REG_BASE : Base address to use for registers.
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// REG_SIZE : Register space size.
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// NUM_DBOARDS : Number of daughterboards to support.
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//
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`default_nettype none
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module x4xx_dio #(
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parameter REG_BASE = 0,
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parameter REG_SIZE = 'h30,
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parameter NUM_DBOARDS = 2
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) (
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// Slave ctrlport interface
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
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output reg [31:0] s_ctrlport_resp_data = {32 {1'bX}},
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// GPIO to DIO board (ctrlport_clk)
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output wire [11:0] gpio_en_a,
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output wire [11:0] gpio_en_b,
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// GPIO to DIO board (async)
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input wire [11:0] gpio_in_a,
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input wire [11:0] gpio_in_b,
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output wire [11:0] gpio_out_a,
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output wire [11:0] gpio_out_b,
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// ATR GPIO Control (ctrlport_clk)
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input wire [NUM_DBOARDS*32-1:0] atr_gpio_out,
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input wire [NUM_DBOARDS*32-1:0] atr_gpio_ddr,
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// PS GPIO Control from Block Design (async)
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input wire [31:0] ps_gpio_out,
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input wire [31:0] ps_gpio_ddr,
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// Digital Interface Control (ctrlport_clk)
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input wire [31:0] digital_ifc_gpio_out_radio0,
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input wire [31:0] digital_ifc_gpio_ddr_radio0,
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input wire [31:0] digital_ifc_gpio_out_radio1,
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input wire [31:0] digital_ifc_gpio_ddr_radio1,
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// GPIO to user application (async)
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// User application relies on the local direction register
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// for GPIO direction control. For this reason, we skip
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// a mux to select between the user application and the
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// local register direction control in the mux chain, and
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// propagate their shared direction(from the local register)
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// to the remainder of the mux chain.
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output wire [11:0] user_app_in_a,
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output wire [11:0] user_app_in_b,
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input wire [11:0] user_app_out_a,
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input wire [11:0] user_app_out_b
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/dio_regmap_utils.vh"
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//---------------------------------------------------------------------------
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// Constants
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//---------------------------------------------------------------------------
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localparam DIO_WIDTH = 12;
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//---------------------------------------------------------------------------
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// DIO Registers
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//---------------------------------------------------------------------------
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reg [DIO_WIDTH-1:0] dio_direction_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_direction_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_master_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_master_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_output_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_output_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_source_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_source_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_radio_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_radio_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_interface_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_interface_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_override_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_override_b = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_sw_ctrl_a = {DIO_WIDTH {1'b0}};
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reg [DIO_WIDTH-1:0] dio_sw_ctrl_b = {DIO_WIDTH {1'b0}};
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wire [DIO_WIDTH-1:0] dio_input_a;
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wire [DIO_WIDTH-1:0] dio_input_b;
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//---------------------------------------------------------------------------
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// Control interface handling
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//---------------------------------------------------------------------------
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// Check that address is within this module's range.
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wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= {32 {1'bX}};
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s_ctrlport_resp_status <= 2'b00;
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dio_direction_a <= {DIO_WIDTH {1'b0}};
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dio_direction_b <= {DIO_WIDTH {1'b0}};
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dio_master_a <= {DIO_WIDTH {1'b0}};
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dio_master_b <= {DIO_WIDTH {1'b0}};
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dio_output_a <= {DIO_WIDTH {1'b0}};
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dio_output_b <= {DIO_WIDTH {1'b0}};
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dio_source_a <= {DIO_WIDTH {1'b0}};
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dio_source_b <= {DIO_WIDTH {1'b0}};
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dio_radio_a <= {DIO_WIDTH {1'b0}};
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dio_radio_b <= {DIO_WIDTH {1'b0}};
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dio_interface_a <= {DIO_WIDTH {1'b0}};
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dio_interface_b <= {DIO_WIDTH {1'b0}};
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dio_override_a <= {DIO_WIDTH {1'b0}};
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dio_override_b <= {DIO_WIDTH {1'b0}};
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dio_sw_ctrl_a <= {DIO_WIDTH {1'b0}};
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dio_sw_ctrl_b <= {DIO_WIDTH {1'b0}};
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end else begin
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// Write registers
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if (s_ctrlport_req_wr) begin
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// Acknowledge by default
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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REG_BASE + DIO_MASTER_REGISTER: begin
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dio_master_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_master_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + DIO_DIRECTION_REGISTER: begin
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dio_direction_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_direction_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + DIO_OUTPUT_REGISTER: begin
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dio_output_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_output_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + DIO_SOURCE_REGISTER: begin
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dio_source_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_source_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + RADIO_SOURCE_REGISTER: begin
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dio_radio_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_radio_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + INTERFACE_DIO_SELECT: begin
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dio_interface_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_interface_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + DIO_OVERRIDE: begin
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dio_override_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_override_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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REG_BASE + SW_DIO_CONTROL: begin
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dio_sw_ctrl_a <= s_ctrlport_req_data[DIO_PORT_A_MSB:DIO_PORT_A];
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dio_sw_ctrl_b <= s_ctrlport_req_data[DIO_PORT_B_MSB:DIO_PORT_B];
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// Read registers
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end else if (s_ctrlport_req_rd) begin
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// Acknowledge by default
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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REG_BASE + DIO_MASTER_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_master_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_master_b;
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end
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REG_BASE + DIO_DIRECTION_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_direction_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_direction_b;
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end
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REG_BASE + DIO_OUTPUT_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_output_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_output_b;
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end
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REG_BASE + DIO_INPUT_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_input_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_input_b;
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end
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REG_BASE + DIO_SOURCE_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_source_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_source_b;
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end
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REG_BASE + RADIO_SOURCE_REGISTER: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_radio_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_radio_b;
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end
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REG_BASE + INTERFACE_DIO_SELECT: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_interface_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_interface_b;
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end
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REG_BASE + DIO_OVERRIDE: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_override_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_override_b;
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end
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REG_BASE + SW_DIO_CONTROL: begin
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s_ctrlport_resp_data[DIO_PORT_A_MSB:DIO_PORT_A] <= dio_sw_ctrl_a;
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s_ctrlport_resp_data[DIO_PORT_B_MSB:DIO_PORT_B] <= dio_sw_ctrl_b;
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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//---------------------------------------------------------------------------
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// DIO handling
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//---------------------------------------------------------------------------
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// Synchronizer for asynchronous inputs.
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// Downstream user logic has to ensure bus coherency if required.
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synchronizer #(
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.WIDTH (DIO_WIDTH*2),
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.STAGES (2),
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.INITIAL_VAL ({DIO_WIDTH*2 {1'b0}}),
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.FALSE_PATH_TO_IN (1)
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) synchronizer_dio (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.in ({gpio_in_a, gpio_in_b}),
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.out ({dio_input_a, dio_input_b})
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);
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// Forward raw input to user application
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assign user_app_in_a = gpio_in_a;
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assign user_app_in_b = gpio_in_b;
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wire [DIO_WIDTH-1:0] gpio_out_sw_a;
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wire [DIO_WIDTH-1:0] gpio_out_sw_b;
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// Output assignment depending on master
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generate
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genvar i;
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for (i = 0; i < DIO_WIDTH; i = i + 1) begin: dio_output_gen
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reg atr_gpio_src_out_a_reg = 1'b0;
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reg atr_gpio_src_out_b_reg = 1'b0;
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reg atr_gpio_src_ddr_a_reg = 1'b0;
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reg atr_gpio_src_ddr_b_reg = 1'b0;
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// 1) Select which radio drives the output
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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atr_gpio_src_out_a_reg <= 1'b0;
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atr_gpio_src_out_b_reg <= 1'b0;
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end else begin
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atr_gpio_src_out_a_reg <= atr_gpio_out[dio_radio_a[i]*32 + DIO_PORT_A + i];
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atr_gpio_src_out_b_reg <= atr_gpio_out[dio_radio_b[i]*32 + DIO_PORT_B + i];
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end
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end
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// 2) Select which radio drives the direction
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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atr_gpio_src_ddr_a_reg <= 1'b0;
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atr_gpio_src_ddr_b_reg <= 1'b0;
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end else begin
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atr_gpio_src_ddr_a_reg <= atr_gpio_ddr[dio_radio_a[i]*32 + DIO_PORT_A + i];
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atr_gpio_src_ddr_b_reg <= atr_gpio_ddr[dio_radio_b[i]*32 + DIO_PORT_B + i];
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end
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end
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// Select between the Digital Interface in each radio(INTERFACE_DIO_SELECT)
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wire dio_interface_mux_out_a;
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wire dio_interface_mux_out_b;
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wire dio_interface_mux_ddr_a;
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wire dio_interface_mux_ddr_b;
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glitch_free_mux glitch_free_interface_out_mux_dio_a (
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.select (dio_interface_a[i]),
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.signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_A + i]),
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.signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_A + i]),
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.muxed_signal (dio_interface_mux_out_a)
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);
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glitch_free_mux glitch_free_interface_out_mux_dio_b (
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.select (dio_interface_b[i]),
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.signal0 (digital_ifc_gpio_out_radio0[DIO_PORT_B + i]),
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.signal1 (digital_ifc_gpio_out_radio1[DIO_PORT_B + i]),
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.muxed_signal (dio_interface_mux_out_b)
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);
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glitch_free_mux glitch_free_interface_ddr_mux_dio_a (
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.select (dio_interface_a[i]),
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.signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_A + i]),
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.signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_A + i]),
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.muxed_signal (dio_interface_mux_ddr_a)
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);
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glitch_free_mux glitch_free_interface_ddr_mux_dio_b (
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.select (dio_interface_b[i]),
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.signal0 (digital_ifc_gpio_ddr_radio0[DIO_PORT_B + i]),
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.signal1 (digital_ifc_gpio_ddr_radio1[DIO_PORT_B + i]),
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.muxed_signal (dio_interface_mux_ddr_b)
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);
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// Select between ATR or Digital control(DIO_OVERRIDE)
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wire dio_override_mux_out_a;
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wire dio_override_mux_out_b;
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wire dio_override_mux_ddr_a;
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wire dio_override_mux_ddr_b;
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glitch_free_mux glitch_free_override_out_mux_dio_a (
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.select (dio_override_a[i]),
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.signal0 (atr_gpio_src_out_a_reg),
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.signal1 (dio_interface_mux_out_a),
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.muxed_signal (dio_override_mux_out_a)
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);
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glitch_free_mux glitch_free_override_out_mux_dio_b (
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.select (dio_override_b[i]),
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.signal0 (atr_gpio_src_out_b_reg),
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.signal1 (dio_interface_mux_out_b),
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.muxed_signal (dio_override_mux_out_b)
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);
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glitch_free_mux glitch_free_override_ddr_mux_dio_a (
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.select (dio_override_a[i]),
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.signal0 (atr_gpio_src_ddr_a_reg),
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.signal1 (dio_interface_mux_ddr_a),
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.muxed_signal (dio_override_mux_ddr_a)
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);
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glitch_free_mux glitch_free_override_ddr_mux_dio_b (
|
|
.select (dio_override_b[i]),
|
|
.signal0 (atr_gpio_src_ddr_b_reg),
|
|
.signal1 (dio_interface_mux_ddr_b),
|
|
.muxed_signal (dio_override_mux_ddr_b)
|
|
);
|
|
|
|
|
|
// SW source select
|
|
// SW_DIO_CONTROL, select between PS and local register
|
|
|
|
wire dio_sw_control_mux_out_a;
|
|
wire dio_sw_control_mux_out_b;
|
|
wire dio_sw_control_mux_ddr_a;
|
|
wire dio_sw_control_mux_ddr_b;
|
|
|
|
glitch_free_mux glitch_free_sw_control_out_mux_dio_a (
|
|
.select (dio_sw_ctrl_a[i]),
|
|
.signal0 (dio_output_a[i]),
|
|
.signal1 (ps_gpio_out[DIO_PORT_A + i]),
|
|
.muxed_signal (dio_sw_control_mux_out_a)
|
|
);
|
|
|
|
glitch_free_mux glitch_free_sw_control_out_mux_dio_b (
|
|
.select (dio_sw_ctrl_b[i]),
|
|
.signal0 (dio_output_b[i]),
|
|
.signal1 (ps_gpio_out[DIO_PORT_B + i]),
|
|
.muxed_signal (dio_sw_control_mux_out_b)
|
|
);
|
|
|
|
glitch_free_mux glitch_free_sw_control_ddr_mux_dio_a (
|
|
.select (dio_sw_ctrl_a[i]),
|
|
.signal0 (dio_direction_a[i]),
|
|
.signal1 (ps_gpio_ddr[DIO_PORT_A + i]),
|
|
.muxed_signal (dio_sw_control_mux_ddr_a)
|
|
);
|
|
|
|
glitch_free_mux glitch_free_sw_control_ddr_mux_dio_b (
|
|
.select (dio_sw_ctrl_b[i]),
|
|
.signal0 (dio_direction_b[i]),
|
|
.signal1 (ps_gpio_ddr[DIO_PORT_B + i]),
|
|
.muxed_signal (dio_sw_control_mux_ddr_b)
|
|
);
|
|
|
|
|
|
// DIO_MASTER_REGISTER Mux, select between SW_DIO_CONTROL
|
|
// and user application
|
|
// User application relies on the local direction register
|
|
// for GPIO direction control. For this reason, we skip
|
|
// a mux to select between the user application and the
|
|
// local register direction control in the mux chain, and
|
|
// propagate their shared direction(from the local register)
|
|
// to the remainder of the mux chain.
|
|
glitch_free_mux glitch_free_master_mux_dio_a (
|
|
.select (dio_master_a[i]),
|
|
.signal0 (user_app_out_a[i]),
|
|
.signal1 (dio_sw_control_mux_out_a),
|
|
.muxed_signal (gpio_out_sw_a[i])
|
|
);
|
|
|
|
glitch_free_mux glitch_free_master_mux_dio_b (
|
|
.select (dio_master_b[i]),
|
|
.signal0 (user_app_out_b[i]),
|
|
.signal1 (dio_sw_control_mux_out_b),
|
|
.muxed_signal (gpio_out_sw_b[i])
|
|
);
|
|
|
|
// DIO_SOURCE_REGISTER mux, select between (DIO_MASTER_REGISTER output) and
|
|
// radio controlled source (DIO_OVERRIDE output).
|
|
glitch_free_mux glitch_free_source_out_mux_dio_a (
|
|
.select (dio_source_a[i]),
|
|
.signal0 (gpio_out_sw_a[i]),
|
|
.signal1 (dio_override_mux_out_a),
|
|
.muxed_signal (gpio_out_a[i])
|
|
);
|
|
|
|
glitch_free_mux glitch_free_source_out_mux_dio_b (
|
|
.select (dio_source_b[i]),
|
|
.signal0 (gpio_out_sw_b[i]),
|
|
.signal1 (dio_override_mux_out_b),
|
|
.muxed_signal (gpio_out_b[i])
|
|
);
|
|
|
|
// Direction control
|
|
glitch_free_mux glitch_free_dir_mux_dio_a (
|
|
.select (dio_source_a[i]),
|
|
.signal0 (dio_sw_control_mux_ddr_a),
|
|
.signal1 (dio_override_mux_ddr_a),
|
|
.muxed_signal (gpio_en_a[i])
|
|
);
|
|
|
|
glitch_free_mux glitch_free_dir_mux_dio_b (
|
|
.select (dio_source_b[i]),
|
|
.signal0 (dio_sw_control_mux_ddr_b),
|
|
.signal1 (dio_override_mux_ddr_b),
|
|
.muxed_signal (gpio_en_b[i])
|
|
);
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
|
|
`default_nettype wire
|
|
|
|
|
|
//XmlParse xml_on
|
|
//<regmap name="DIO_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
|
// <group name="DIO_REGS">
|
|
// <info>
|
|
// Registers to control the GPIO buffer direction on the FPGA connected to
|
|
// the DIO board. Further registers enable different sources to control and
|
|
// read the GPIO lines as master. The following diagram shows how source
|
|
// selection multiplexers are arranged, as well as an indicator for the
|
|
// register that control them. </br>
|
|
// <img src = "..\..\..\..\..\host\docs\res\x4xx_dio_source_muxes.svg"
|
|
// alt="Front-Panel Programmable GPIOs"/></br>
|
|
// Make sure the GPIO lines between FPGA and GPIO board are not driven by
|
|
// two drivers. Set the DIO registers in @.PS_CPLD_BASE_REGMAP appropriately.
|
|
// </info>
|
|
//
|
|
// <regtype name="DIO_CONTROL_REG" size="32">
|
|
// <info>
|
|
// Holds a single bit setting for DIO lines in both ports. One bit per pin.
|
|
// </info>
|
|
// <bitfield name="DIO_PORT_A" range="0..11" initialvalue="0"/>
|
|
// <bitfield name="DIO_PORT_B" range="16..27" initialvalue="0"/>
|
|
// </regtype>
|
|
//
|
|
// <register name="DIO_MASTER_REGISTER" offset="0x00" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Sets whether the DIO signal line is driven by this register interface
|
|
// or the user application.{br/}
|
|
// 0 = user application is master, 1 = output of @.SW_DIO_CONTROL is master
|
|
// </info>
|
|
// </register>
|
|
// <register name="DIO_DIRECTION_REGISTER" offset="0x04" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Set the direction of FPGA buffer connected to DIO ports on the DIO board.{br/}
|
|
// Each bit represents one signal line. 0 = line is an input to the FPGA,
|
|
// 1 = line is an output driven by the FPGA.
|
|
// </info>
|
|
// </register>
|
|
// <register name="DIO_INPUT_REGISTER" offset="0x08" typename="DIO_CONTROL_REG" writable="false">
|
|
// <info>
|
|
// Status of each bit at the FPGA input.
|
|
// </info>
|
|
// </register>
|
|
// <register name="DIO_OUTPUT_REGISTER" offset="0x0C" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls the values on each DIO signal line in case the line master is
|
|
// set to PS in @.DIO_MASTER_REGISTER.
|
|
// </info>
|
|
// </register>
|
|
// <register name="DIO_SOURCE_REGISTER" offset="0x10" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls whether the DIO lines reflect the state of @.DIO_MASTER_REGISTER
|
|
// or the radio blocks. 0 = @.DIO_MASTER_REGISTER,
|
|
// 1 = Radio block output(@.DIO_OVERRIDE)
|
|
// </info>
|
|
// </register>
|
|
// <register name="RADIO_SOURCE_REGISTER" offset="0x14" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls which radio block to use the ATR state from to determine the
|
|
// state of the DIO lines.
|
|
// 0 = Radio#0
|
|
// 1 = Radio#1
|
|
// </info>
|
|
// </register>
|
|
// <register name="INTERFACE_DIO_SELECT" offset="0x18" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls which of the two available digital interfaces controls the DIO lines.
|
|
// 0 = Digital interface from Radio#0,
|
|
// 1 = Digital Interface from Radio#1.
|
|
// </info>
|
|
// </register>
|
|
// <register name="DIO_OVERRIDE" offset="0x1C" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls whether the radio input to the @.DIO_SOURCE_REGISTER mux
|
|
// connects to the ATR control or a Digital interface block. The output
|
|
// of the mux controlled by this bit goes to @.DIO_SOURCE_REGISTER.
|
|
// 0 = Drive the ATR state(@.RADIO_SOURCE_REGISTER), 1 = Drive
|
|
// Digital interface block(Output of @.INTERFACE_DIO_SELECT).
|
|
// </info>
|
|
// </register>
|
|
// <register name="SW_DIO_CONTROL" offset="0x20" typename="DIO_CONTROL_REG">
|
|
// <info>
|
|
// Controls which source is forwarded to the @.DIO_MASTER_REGISTER mux.
|
|
// This configuration is applied independently for each DIO line.
|
|
// 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
|
|
// </info>
|
|
// </register>
|
|
// </group>
|
|
//</regmap>
|
|
//XmlParse xml_off
|