5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
302 lines
9.9 KiB
Verilog
302 lines
9.9 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: pl_cpld_regs
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//
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// Description:
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//
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// Basic Registers to inform software about version and capabilities.
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//
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// Parameters:
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//
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// BASE_ADDRESS : Base address for CtrlPort registers
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//
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`default_nettype none
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module pl_cpld_regs #(
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parameter BASE_ADDRESS = 0
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// QSFP LEDs
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// Port 0
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output wire [ 3:0] qsfp0_led_active,
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output wire [ 3:0] qsfp0_led_link,
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// Port 1
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output wire [ 3:0] qsfp1_led_active,
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output wire [ 3:0] qsfp1_led_link,
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// iPass status
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output wire [ 1:0] ipass_cable_present
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);
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`ifdef X410
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`include "../regmap/x410/constants_regmap_utils.vh"
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`else
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`include "../regmap/x440/constants_regmap_utils.vh"
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`endif
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`include "../regmap/pl_cpld_base_regmap_utils.vh"
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`include "../../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------------------
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// Address Calculation
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//---------------------------------------------------------------------------
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localparam NUM_ADDRESSES = 64;
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
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(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
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//---------------------------------------------------------------------------
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// Internal Registers
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//---------------------------------------------------------------------------
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reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;
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reg [LED_REGISTER_SIZE-1:0] led_reg;
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reg [CABLE_PRESENT_REG_SIZE-1:0] ipass_reg;
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//---------------------------------------------------------------------------
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// Assign Outputs
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//---------------------------------------------------------------------------
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assign qsfp0_led_active = led_reg[QSFP0_LED_ACTIVE+:QSFP0_LED_ACTIVE_SIZE];
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assign qsfp0_led_link = led_reg[QSFP0_LED_LINK+:QSFP0_LED_LINK_SIZE];
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assign qsfp1_led_active = led_reg[QSFP1_LED_ACTIVE+:QSFP1_LED_ACTIVE_SIZE];
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assign qsfp1_led_link = led_reg[QSFP1_LED_LINK+:QSFP1_LED_LINK_SIZE];
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assign ipass_cable_present = ipass_reg;
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//---------------------------------------------------------------------------
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// Handling of ControlPort Requests
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//---------------------------------------------------------------------------
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always @(posedge ctrlport_clk) begin
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// Reset internal registers and responses
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if (ctrlport_rst) begin
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scratch_reg <= 0;
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led_reg <= 0;
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ipass_reg <= 0;
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s_ctrlport_resp_ack <= 1'b0;
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// Write requests
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end else if (s_ctrlport_req_wr) begin
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// Always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SCRATCH_REGISTER:
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scratch_reg <= s_ctrlport_req_data;
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BASE_ADDRESS + LED_REGISTER:
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led_reg <= s_ctrlport_req_data[LED_REGISTER_SIZE-1:0];
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BASE_ADDRESS + CABLE_PRESENT_REG: begin
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ipass_reg[0] <= s_ctrlport_req_data[IPASS0_CABLE_PRESENT];
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ipass_reg[1] <= s_ctrlport_req_data[IPASS1_CABLE_PRESENT];
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end
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// Error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// Read request
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end else if (s_ctrlport_req_rd) begin
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// Default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SIGNATURE_REGISTER:
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s_ctrlport_resp_data <= PL_CPLD_SIGNATURE;
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BASE_ADDRESS + REVISION_REGISTER:
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s_ctrlport_resp_data <= CPLD_REVISION;
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BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
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s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;
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BASE_ADDRESS + SCRATCH_REGISTER:
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s_ctrlport_resp_data <= scratch_reg;
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BASE_ADDRESS + GIT_HASH_REGISTER:
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`ifdef GIT_HASH
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s_ctrlport_resp_data <= `GIT_HASH;
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`else
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s_ctrlport_resp_data <= 32'hDEADBEEF;
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`endif
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BASE_ADDRESS + LED_REGISTER:
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s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - LED_REGISTER_SIZE){1'b0}}, led_reg};
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BASE_ADDRESS + CABLE_PRESENT_REG: begin
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
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s_ctrlport_resp_data[IPASS0_CABLE_PRESENT] <= ipass_reg[0];
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s_ctrlport_resp_data[IPASS1_CABLE_PRESENT] <= ipass_reg[1];
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end
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// Error on undefined address
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default: begin
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s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// No request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="PL_CPLD_BASE_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="PL_CPLD_BASE_REGS">
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// <info>
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// Basic registers containing version and capabilities information.
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// </info>
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//
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// <register name="SIGNATURE_REGISTER" offset="0x00" writable="false" size="32">
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// <info>Contains the product's signature.</info>
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// <bitfield name="PRODUCT_SIGNATURE" range="31..0">
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// <info>Fixed value PL_CPLD_SIGNATURE of @.CONSTANTS_REGMAP</info>
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// </bitfield>
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// </register>
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//
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// <register name="REVISION_REGISTER" offset="0x04" writable="false" size="32">
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// <info>Contains the CPLD revision (see CPLD_REVISION of @.CONSTANTS_REGMAP)</info>
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// <bitfield name="REVISION_HH" range="7..0">
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// <info>Contains revision hour code.</info>
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// </bitfield>
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// <bitfield name="REVISION_DD" range="15..8">
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// <info>Contains revision day code.</info>
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// </bitfield>
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// <bitfield name="REVISION_MM" range="23..16">
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// <info>Contains revision month code.</info>
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// </bitfield>
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// <bitfield name="REVISION_YY" range="31..24">
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// <info>Contains revision year code.</info>
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// </bitfield>
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// </register>
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//
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// <register name="OLDEST_COMPATIBLE_REVISION_REGISTER" offset="0x08" writable="false" size="32">
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// <info>
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// This register returns (in YYMMDDHH format) the oldest revision
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// that is still compatible with this one. Compatible means that
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// registers or register bits may have been added, but not
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// modified or deleted (see OLDEST_CPLD_REVISION of @.CONSTANTS_REGMAP).
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// </info>
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// <bitfield name="OLD_REVISION_HH" range="7..0">
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// <info>Contains revision hour code.</info>
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// </bitfield>
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// <bitfield name="OLD_REVISION_DD" range="15..8">
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// <info>Contains revision day code.</info>
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// </bitfield>
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// <bitfield name="OLD_REVISION_MM" range="23..16">
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// <info>Contains revision month code.</info>
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// </bitfield>
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// <bitfield name="OLD_REVISION_YY" range="31..24">
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// <info>Contains revision year code.</info>
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// </bitfield>
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// </register>
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//
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// <register name="SCRATCH_REGISTER" offset="0x0C" size="32">
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// <info>Read/write register for general software use.</info>
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// </register>
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//
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// <register name="GIT_HASH_REGISTER" offset="0x10" size="32" writable="false">
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// <info>
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// Git hash of commit used to build this image.{br}
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// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
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// </info>
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// <bitfield name="GIT_CLEAN" range="31..28">
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// <info>
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// 0x0 in case the git status was clean{br}
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// 0xF in case there were uncommitted changes
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// </info>
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// </bitfield>
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// <bitfield name="GIT_HASH" range="27..0">
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// <info>7 hex digit hash code of the commit</info>
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// </bitfield>
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// </register>
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// </group>
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//
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// <group name="MB_CPLD_LED_REGS">
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// <info>
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// Register Map to control QSFP LEDs.
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// </info>
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// <register name="LED_REGISTER" offset="0x20" size="16">
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// <info>
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// Provides to the LEDs of the QSFP ports.
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// Write access will directly change the LED status.
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// The LED lights up if the corresponding bit is set.
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// </info>
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// <bitfield name="QSFP0_LED_LINK" range="3..0">
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// <info>Link LEDs of QSFP port 0</info>
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// </bitfield>
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// <bitfield name="QSFP0_LED_ACTIVE" range="7..4">
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// <info>Active LEDs of QSFP port 0</info>
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// </bitfield>
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// <bitfield name="QSFP1_LED_LINK" range="11..8">
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// <info>Link LEDs of QSFP port 1</info>
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// </bitfield>
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// <bitfield name="QSFP1_LED_ACTIVE" range="15..12">
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// <info>Active LEDs of QSFP port 1</info>
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// </bitfield>
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// </register>
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// </group>
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//
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// <group name="PL_CMI_REGS">
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// <info>
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// Cable present status register.
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// </info>
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// <register name="CABLE_PRESENT_REG" offset="0x30" size="2">
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// <info>
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// Information from FPGA about the cable present status.
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// </info>
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// <bitfield name="IPASS0_CABLE_PRESENT" range="0">
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// <info>Set to 1 if cable present in iPass 0 connector.</info>
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// </bitfield>
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// <bitfield name="IPASS1_CABLE_PRESENT" range="1">
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// <info>Set to 1 if cable present in iPass 1 connector.</info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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