5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
22 lines
874 B
Tcl
22 lines
874 B
Tcl
#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440 400 type images
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#
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# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
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# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
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# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
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set rfdc_data_clk_period 15.625
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create_clock -name rfdc_r0_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
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create_clock -name rfdc_r1_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
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