37 lines
1.0 KiB
PHP
37 lines
1.0 KiB
PHP
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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PROJECT_DIR = $(abspath .)
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BASE_DIR = $(abspath ../../../..)
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include $(BASE_DIR)/../tools/make/quartus_design_builder.mak
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# Define VERILOG_DEFS for macros definition
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VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF)
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bin: .prereqs
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$(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),,0)
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@\
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pushd $(BUILD_DIR); \
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echo "Converting bitfile to svf format..."; \
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quartus_cpf --convert \
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--frequency 10.0MHz \
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--voltage 2.5 \
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--operation p \
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output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE).svf; \
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popd;
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