Wade Fife 7e3f04d0ab fpga: e320: Update AXI interconnect address range ...

This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: d352f5a9c3bd3791f0320be1e615146fe7459453

2020-08-28 15:07:38 -05:00

..

aurora_64b66b_pcs_pma

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi64_4k_2clk_fifo

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi64_8k_2clk_fifo

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi_eth_dma

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi_intercon_4x64_256_bd

fpga: e320: Update AXI interconnect address range

2020-08-28 15:07:38 -05:00

ddr3_32bit

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_ps_bd

e320: Swap out liberio for internal Ethernet

2020-07-16 10:00:12 -05:00

fifo_4k_2clk

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

fifo_short_2clk

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

one_gig_eth_pcs_pma

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ten_gig_eth_pcs_pma

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile.inc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00