44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module pcie_pkt_route_specifier #(
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parameter BASE_ADDR = 20'h0,
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parameter ADDR_MASK = 20'hFFF00,
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parameter SID_WIDTH = 8,
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parameter DST_WIDTH = 4
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) (
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input clk,
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input reset,
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input [63:0] regi_tdata,
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input regi_tvalid,
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output regi_tready,
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input [SID_WIDTH-1:0] local_sid,
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output [DST_WIDTH-1:0] fifo_dst
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);
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// Routing table
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reg [DST_WIDTH-1:0] routing_table[0:(1<<SID_WIDTH)-1];
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assign fifo_dst = routing_table[local_sid];
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wire reg_wr;
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wire [19:0] reg_addr;
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wire [31:0] reg_data;
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// Routing table configuration
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ioport2_msg_decode config_message_decoder (
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.message(regi_tdata), .wr_request(reg_wr), .rd_request(reg_rd), .address(reg_addr), .data(reg_data)
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);
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always @(posedge clk) begin
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if (regi_tvalid && regi_tready && reg_wr && ((reg_addr & ADDR_MASK) == BASE_ADDR)) begin
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routing_table[reg_data[SID_WIDTH+15:16]] <= reg_data[DST_WIDTH-1:0];
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end
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end
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assign regi_tready = 1;
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endmodule
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