105 lines
2.6 KiB
Verilog
105 lines
2.6 KiB
Verilog
`timescale 1ns/1ps
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module radio_ctrl_proc_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("radio_ctrl_proc_tb.vcd");
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initial $dumpvars(0,radio_ctrl_proc_tb);
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initial
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begin
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#1000 reset = 0;
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#20000;
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$finish;
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end
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reg [63:0] vita_time = 64'd0;
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always @(posedge clk)
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if(reset) vita_time <= 64'd0;
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else vita_time <= vita_time + 64'd1;
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reg [63:0] tdata;
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wire [63:0] tdata_int;
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reg tlast;
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wire tlast_int;
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reg tvalid = 1'b0;
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wire tvalid_int;
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wire tready, tready_int;
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wire [7:0] set_addr;
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wire [31:0] set_data;
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wire set_stb;
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wire ready = 1'b1;
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task send_packet;
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input ec;
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input timed;
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input [11:0] seqnum;
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input [31:0] sid;
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input [63:0] vtime;
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input [15:0] addr;
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input [31:0] data;
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begin
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// Send a packet
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@(posedge clk);
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tlast <= 1'b0;
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tdata <= { ec, 1'b0, timed, 1'b0, seqnum, timed ? 16'd6 : 16'd4, sid };
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tvalid <= 1;
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@(posedge clk);
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if(timed)
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begin
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tdata <= vtime;
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@(posedge clk);
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end
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tlast <= 1'b1;
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tdata <= { 16'h0, addr, data };
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@(posedge clk);
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tvalid <= 0;
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@(posedge clk);
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end
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endtask // send_packet
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initial
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begin
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tvalid <= 1'b0;
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while(reset)
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@(posedge clk);
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send_packet(1'b1,1'b0,12'h5,32'hDEAD_BEEF,64'h0,16'hB,32'hF00D_1234);
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send_packet(1'b1,1'b1,12'h6,32'hDEAD_6789,64'h20,16'hC,32'hABCD_4321);
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send_packet(1'b1,1'b1,12'h7,32'hDEAD_6789,64'h30,16'hC,32'hABCD_4321);
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//send_packet(.ec(1), .timed(0), .seqnum(5), .sid(32'hDEAD_BEEF), .vtime(0), .addr(16'hB), .data(32'hF00D_1234));
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end
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axi_fifo_short #(.WIDTH(65)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({tlast,tdata}), .i_tvalid(tvalid), .i_tready(tready),
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.o_tdata({tlast_int,tdata_int}), .o_tvalid(tvalid_int), .o_tready(tready_int));
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wire [63:0] resp_tdata;
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wire resp_tlast, resp_tvalid, resp_tready;
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radio_ctrl_proc radio_ctrl_proc
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(.clk(clk), .reset(reset), .clear(1'b0),
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.ctrl_tdata(tdata_int), .ctrl_tlast(tlast_int), .ctrl_tvalid(tvalid_int), .ctrl_tready(tready_int),
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.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
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.vita_time(vita_time), .ready(ready),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.debug()
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);
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assign resp_tready = 1'b1;
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always @(posedge clk)
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if(resp_tvalid & resp_tready)
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begin
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$display("%x",resp_tdata);
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if(resp_tlast)
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$display("TLAST");
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end
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endmodule // radio_ctrl_proc_tb
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