Martin Braun 471173f245 fpga: e320: Connect CTRL_IN pins to FPGA ...

These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).


Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e

2022-01-10 08:46:56 -06:00

..

dts

e320: Swap out liberio for internal Ethernet

2020-07-16 10:00:12 -05:00

ip

fpga: e320: Update AXI interconnect address range

2020-08-28 15:07:38 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build_e320.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

dev_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_1ge.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_10ge_port0.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_10ge.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_aurora.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_clocking.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_core.v

fpga: Update DRAM IO signatures

2020-09-03 15:26:33 -05:00

e320_dram.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320_rfnoc_image_core.v

fpga: Update rfnoc_image_core for all targets

2021-06-10 11:56:58 -05:00

e320_rfnoc_image_core.vh

fpga: Update rfnoc_image_core for all targets

2021-06-10 11:56:58 -05:00

e320_rfnoc_image_core.yml

fpga: Change RFNoC YAML version numbers to strings

2021-06-08 15:48:59 -05:00

e320_static_router.hex

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e320.v

fpga: e320: Connect CTRL_IN pins to FPGA

2022-01-10 08:46:56 -06:00

Makefile

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile.e320.inc

E320: Revert addition of Replay block

2020-09-04 15:45:51 -07:00

mb_pins.xdc

fpga: e320: Connect CTRL_IN pins to FPGA

2022-01-10 08:46:56 -06:00

mb_timing.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_mgt_io_core.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

n3xx_sfp_wrapper.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

setupenv.sh

fpga: Set default part for sim in setupenv.sh

2021-08-30 08:20:10 -05:00