Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
8 lines
301 B
Plaintext
8 lines
301 B
Plaintext
NET ETH_CLK_p IOSTANDARD = LVDS_25 | LOC = L8;
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NET "ETH_CLK_p" TNM_NET = ETH_CLK_p;
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TIMESPEC TS_ETH_CLK_p = PERIOD "ETH_CLK_p" 8 ns HIGH 50%;
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NET ETH_CLK_n IOSTANDARD = LVDS_25 | LOC = L7;
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NET "ETH_CLK_n" TNM_NET = ETH_CLK_n;
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TIMESPEC TS_ETH_CLK_n = PERIOD "ETH_CLK_n" TS_ETH_CLK_p HIGH 50%;
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