Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
528 lines
19 KiB
Verilog
528 lines
19 KiB
Verilog
//------------------------------------------------------------------------------
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// Title : Top-level Transceiver GT wrapper for Ethernet
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// Project : Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE
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// File : gige_sfp_mdio_transceiver.v
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// Author : Xilinx
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//------------------------------------------------------------------------------
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//------------------------------------------------------------------------------
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// Description: This is the top-level Transceiver GT wrapper. It
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// instantiates the lower-level wrappers produced by
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// the Series-7 FPGA Transceiver GT Wrapper Wizard.
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//------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module gige_sfp_mdio_transceiver (
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input encommaalign,
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input loopback,
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input powerdown,
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input usrclk,
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input usrclk2,
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input data_valid,
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input independent_clock,
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input txreset,
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input [7:0] txdata,
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input txchardispmode,
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input txchardispval,
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input txcharisk,
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input rxreset,
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output reg rxchariscomma,
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output reg rxcharisk,
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output reg [2:0] rxclkcorcnt,
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output reg [7:0] rxdata,
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output reg rxdisperr,
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output reg rxnotintable,
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output reg rxrundisp,
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output reg rxbuferr,
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output reg txbuferr,
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output plllkdet,
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output txoutclk,
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output txn,
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output txp,
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input rxn,
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input rxp,
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input gtrefclk,
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input pmareset,
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input mmcm_locked,
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output resetdone
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);
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//----------------------------------------------------------------------------
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// Signal declarations
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//----------------------------------------------------------------------------
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wire cplllock;
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wire gt_reset_rx;
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wire gt_reset_tx;
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wire resetdone_tx;
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wire resetdone_rx;
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wire pcsreset;
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(* KEEP = "TRUE" *) reg data_valid_reg;
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wire data_valid_reg2;
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wire [2:0] rxbufstatus;
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wire [1:0] txbufstatus;
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reg [2:0] rxbufstatus_reg;
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reg [1:0] txbufstatus_reg;
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wire [1:0] rxclkcorcnt_int;
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reg txpowerdown_reg = 1'b0;
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reg txpowerdown_double = 1'b0;
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reg txpowerdown = 1'b0;
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wire [1:0] txpowerdown_int;
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// signal used to control sampling during bus width conversions
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reg toggle;
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// signals reclocked onto the 62.5MHz userclk source of the GT transceiver
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wire encommaalign_int;
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wire txreset_int;
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wire rxreset_int;
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// Register transmitter signals from the core
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reg [7:0] txdata_reg;
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reg txchardispmode_reg;
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reg txchardispval_reg;
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reg txcharisk_reg;
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// Signals for data bus width doubling on the transmitter path from the core
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// to the GT transceiver
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reg [15:0] txdata_double;
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reg [1:0] txchardispmode_double;
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reg [1:0] txchardispval_double;
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reg [1:0] txcharisk_double;
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// Double width signals reclocked onto the 62.5MHz userclk source of the GT
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// transceiver
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reg [15:0] txdata_int;
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reg [1:0] txchardispmode_int;
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reg [1:0] txchardispval_int;
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reg [1:0] txcharisk_int;
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// Double width signals output from the GT transceiver on the 62.5MHz clock
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// source
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wire [1:0] rxchariscomma_int;
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wire [1:0] rxcharisk_int;
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wire [15:0] rxdata_int;
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wire [1:0] rxdisperr_int;
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wire [1:0] rxnotintable_int;
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wire [1:0] rxrundisp_int;
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// Double width signals reclocked on the GT's 62.5MHz clock source
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reg [1:0] rxchariscomma_reg;
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reg [1:0] rxcharisk_reg;
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reg [15:0] rxdata_reg;
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reg [1:0] rxdisperr_reg;
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reg [1:0] rxnotintable_reg;
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reg [1:0] rxrundisp_reg;
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reg rxpowerdown_reg = 1'b0;
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// Double width signals reclocked onto the 125MHz clock source
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reg [1:0] rxchariscomma_double;
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reg [1:0] rxcharisk_double;
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reg [15:0] rxdata_double;
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reg [1:0] rxdisperr_double;
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reg [1:0] rxnotintable_double;
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reg [1:0] rxrundisp_double;
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reg rxpowerdown_double = 1'b0;
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reg rxpowerdown = 1'b0;
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wire [1:0] rxpowerdown_int;
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assign txpowerdown_int = {2{txpowerdown}};
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assign rxpowerdown_int = {2{rxpowerdown}};
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//---------------------------------------------------------------------------
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// The core works from a 125MHz clock source, the GT transceiver fabric
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// interface works from a 62.5MHz clock source. The following signals
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// sourced by the core therefore need to be reclocked onto the 62.5MHz
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// clock
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//---------------------------------------------------------------------------
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// Reclock encommaalign
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gige_sfp_mdio_reset_sync reclock_encommaalign
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(
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.clk (usrclk),
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.reset_in (encommaalign),
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.reset_out (encommaalign_int)
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);
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// Reclock txreset
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gige_sfp_mdio_reset_sync reclock_txreset
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(
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.clk (usrclk),
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.reset_in (txreset),
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.reset_out (txreset_int)
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);
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// Reclock rxreset
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gige_sfp_mdio_reset_sync reclock_rxreset
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(
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.clk (usrclk),
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.reset_in (rxreset),
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.reset_out (rxreset_int)
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);
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//---------------------------------------------------------------------------
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// toggle signal used to control sampling during bus width conversions
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//---------------------------------------------------------------------------
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always @(posedge usrclk2)
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begin
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if (txreset) begin
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toggle <= 1'b0;
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end
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else begin
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toggle <= !toggle;
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end
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end
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//---------------------------------------------------------------------------
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// The core works from a 125MHz clock source, the GT transceiver fabric
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// interface works from a 62.5MHz clock source. The following signals
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// sourced by the core therefore need to be converted to double width, then
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// resampled on the GT's 62.5MHz clock
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//---------------------------------------------------------------------------
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// Reclock the transmitter signals
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always @(posedge usrclk2)
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begin
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if (txreset) begin
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txdata_reg <= 8'b0;
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txchardispmode_reg <= 1'b0;
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txchardispval_reg <= 1'b0;
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txcharisk_reg <= 1'b0;
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txpowerdown_reg <= 1'b0;
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end
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else begin
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txdata_reg <= txdata;
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txchardispmode_reg <= txchardispmode;
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txchardispval_reg <= txchardispval;
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txcharisk_reg <= txcharisk;
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txpowerdown_reg <= powerdown;
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end
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end
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// Double the data width
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always @(posedge usrclk2)
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begin
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if (txreset) begin
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txdata_double <= 16'b0;
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txchardispmode_double <= 2'b0;
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txchardispval_double <= 2'b0;
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txcharisk_double <= 2'b0;
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txpowerdown_double <= 1'b0;
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end
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else begin
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if (!toggle) begin
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txdata_double[7:0] <= txdata_reg;
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txchardispmode_double[0] <= txchardispmode_reg;
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txchardispval_double[0] <= txchardispval_reg;
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txcharisk_double[0] <= txcharisk_reg;
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txdata_double[15:8] <= txdata;
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txchardispmode_double[1] <= txchardispmode;
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txchardispval_double[1] <= txchardispval;
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txcharisk_double[1] <= txcharisk;
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end
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txpowerdown_double <= txpowerdown_reg;
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end
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end
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// Cross the clock domain
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always @(posedge usrclk)
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begin
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txdata_int <= txdata_double;
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txchardispmode_int <= txchardispmode_double;
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txchardispval_int <= txchardispval_double;
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txcharisk_int <= txcharisk_double;
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txbufstatus_reg <= txbufstatus;
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txpowerdown <= txpowerdown_double;
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end
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//---------------------------------------------------------------------------
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// The core works from a 125MHz clock source, the GT transceiver fabric
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// interface works from a 62.5MHz clock source. The following signals
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// sourced by the GT transceiver therefore need to converted to half width
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//---------------------------------------------------------------------------
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// Sample the double width received data from the GT transsciever on the GT's
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// 62.5MHz clock
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always @(posedge usrclk)
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begin
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rxchariscomma_reg <= rxchariscomma_int;
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rxcharisk_reg <= rxcharisk_int;
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rxdata_reg <= rxdata_int;
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rxdisperr_reg <= rxdisperr_int;
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rxnotintable_reg <= rxnotintable_int;
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rxrundisp_reg <= rxrundisp_int;
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rxbufstatus_reg <= rxbufstatus;
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rxpowerdown <= rxpowerdown_reg;
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end
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// Reclock the double width received data from the GT transsciever onto the
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// 125MHz clock source. Both clock domains are frequency related and are
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// derived from the same MMCM: the Xilinx tools will accont for this.
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always @(posedge usrclk2)
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begin
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if (rxreset) begin
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rxchariscomma_double <= 2'b0;
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rxcharisk_double <= 2'b0;
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rxdata_double <= 16'b0;
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rxdisperr_double <= 2'b0;
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rxnotintable_double <= 2'b0;
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rxrundisp_double <= 2'b0;
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rxpowerdown_double <= 1'b0;
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end
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else if (toggle) begin
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rxchariscomma_double <= rxchariscomma_reg;
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rxcharisk_double <= rxcharisk_reg;
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rxdata_double <= rxdata_reg;
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rxdisperr_double <= rxdisperr_reg;
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rxnotintable_double <= rxnotintable_reg;
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rxrundisp_double <= rxrundisp_reg;
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end
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rxpowerdown_double <= powerdown;
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end
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// Halve the bus width
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always @(posedge usrclk2)
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begin
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if (rxreset) begin
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rxchariscomma <= 1'b0;
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rxcharisk <= 1'b0;
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rxdata <= 8'b0;
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rxdisperr <= 1'b0;
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rxnotintable <= 1'b0;
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rxrundisp <= 1'b0;
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rxpowerdown_reg <= 1'b0;
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end
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else begin
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if (!toggle) begin
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rxchariscomma <= rxchariscomma_double[0];
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rxcharisk <= rxcharisk_double[0];
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rxdata <= rxdata_double[7:0];
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rxdisperr <= rxdisperr_double[0];
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rxnotintable <= rxnotintable_double[0];
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rxrundisp <= rxrundisp_double[0];
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end
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else begin
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rxchariscomma <= rxchariscomma_double[1];
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rxcharisk <= rxcharisk_double[1];
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rxdata <= rxdata_double[15:8];
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rxdisperr <= rxdisperr_double[1];
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rxnotintable <= rxnotintable_double[1];
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rxrundisp <= rxrundisp_double[1];
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end
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rxpowerdown_reg <= rxpowerdown_double;
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end
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end
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//---------------------------------------------------------------------------
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// Instantiate the Series-7 GTX
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//---------------------------------------------------------------------------
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// Direct from the Transceiver Wizard output
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gige_sfp_mdio_GTWIZARD_init #
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(
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.EXAMPLE_SIM_GTRESET_SPEEDUP ("TRUE")
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)
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gtwizard_inst
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(
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.SYSCLK_IN (independent_clock),
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.SOFT_RESET_IN (pmareset),
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.GT0_TX_FSM_RESET_DONE_OUT (),
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.GT0_RX_FSM_RESET_DONE_OUT (),
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.GT0_DATA_VALID_IN (data_valid_reg2),
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//----------------------- Channel - Ref Clock Ports //------------------
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.GT0_GTREFCLK0_IN (gtrefclk),
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//------------------------------ Channel PLL //-------------------------
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.GT0_CPLLFBCLKLOST_OUT (),
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.GT0_CPLLLOCK_OUT (cplllock),
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.GT0_CPLLLOCKDETCLK_IN (independent_clock),
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.GT0_CPLLRESET_IN (pmareset),
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//----------------------------- Eye Scan Ports //-----------------------
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.GT0_EYESCANDATAERROR_OUT (),
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//---------------------- Loopback and Powerdown Ports //----------------
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.GT0_LOOPBACK_IN (3'b0),
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.GT0_RXPD_IN (rxpowerdown_int),
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.GT0_TXPD_IN (txpowerdown_int),
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//----------------------------- Receive Ports --------------------------
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.GT0_RXUSERRDY_IN (mmcm_locked),
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//--------------------- Receive Ports - 8b10b Decoder //----------------
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.GT0_RXCHARISCOMMA_OUT (rxchariscomma_int),
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.GT0_RXCHARISK_OUT (rxcharisk_int),
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.GT0_RXDISPERR_OUT (rxdisperr_int),
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.GT0_RXNOTINTABLE_OUT (rxnotintable_int),
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//----------------- Receive Ports - Clock Correction Ports //-----------
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.GT0_RXCLKCORCNT_OUT (rxclkcorcnt_int),
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//------------- Receive Ports - Comma Detection and Alignment //--------
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.GT0_RXMCOMMAALIGNEN_IN (encommaalign_int),
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.GT0_RXPCOMMAALIGNEN_IN (encommaalign_int),
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//----------------- Receive Ports - RX Data Path interface //-----------
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.GT0_GTRXRESET_IN (gt_reset_rx),
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// .GT0_GTRXRESET_IN (rxreset_int),
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.GT0_RXDATA_OUT (rxdata_int),
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.GT0_RXOUTCLK_OUT (),
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.GT0_RXUSRCLK_IN (usrclk),
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.GT0_RXUSRCLK2_IN (usrclk),
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//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
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.GT0_RXDFELPMRESET_IN (1'b0),
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.GT0_RXMONITOROUT_OUT (),
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.GT0_RXMONITORSEL_IN (2'b0),
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//----- Receive Ports - RX Driver),OOB signalling),Coupling and Eq.),CDR //
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.GT0_GTXRXN_IN (rxn),
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.GT0_GTXRXP_IN (rxp),
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.GT0_RXCDRLOCK_OUT (),
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports //-
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.GT0_RXBUFRESET_IN (rxreset_int),
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.GT0_RXBUFSTATUS_OUT (rxbufstatus),
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//---------------------- Receive Ports - RX PLL Ports //----------------
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.GT0_RXRESETDONE_OUT (resetdone_rx),
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//----------------------------- Transmit Ports -------------------------
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.GT0_TXUSERRDY_IN (mmcm_locked),
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//-------------- Transmit Ports - 8b10b Encoder Control Ports //--------
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.GT0_TXCHARDISPMODE_IN (txchardispmode_int),
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.GT0_TXCHARDISPVAL_IN (txchardispval_int),
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.GT0_TXCHARISK_IN (txcharisk_int),
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//---------------- Transmit Ports - TX Data Path interface //-----------
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.GT0_GTTXRESET_IN (gt_reset_tx),
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// .GT0_GTTXRESET_IN (txreset_int),
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.GT0_TXDATA_IN (txdata_int),
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.GT0_TXOUTCLK_OUT (txoutclk),
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.GT0_TXOUTCLKFABRIC_OUT (),
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.GT0_TXOUTCLKPCS_OUT (),
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//.GT0_TXPCSRESET_IN (pcsreset),
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.GT0_TXUSRCLK_IN (usrclk),
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.GT0_TXUSRCLK2_IN (usrclk),
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//-------------- Transmit Ports - TX Driver and OOB signaling //--------
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.GT0_GTXTXN_OUT (txn),
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.GT0_GTXTXP_OUT (txp),
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//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment //---
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.GT0_TXBUFSTATUS_OUT (txbufstatus),
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//--------------------- Transmit Ports - TX PLL Ports //----------------
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.GT0_TXRESETDONE_OUT (resetdone_tx),
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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.GT0_TXELECIDLE_IN (txpowerdown),
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//____________________________COMMON PORTS________________________________
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//-------------------- Common Block - Ref Clock Ports ---------------------
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.GT0_GTREFCLK0_COMMON_IN (gtrefclk),
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//----------------------- Common Block - QPLL Ports ------------------------
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.GT0_QPLLLOCK_OUT () ,
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.GT0_QPLLLOCKDETCLK_IN (independent_clock),
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.GT0_QPLLRESET_IN (1'b0)
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);
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// Hold the transmitter and receiver paths of the GT transceiver in reset
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// until the PLL has locked.
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assign gt_reset_rx = (rxreset_int & resetdone_rx);
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assign gt_reset_tx = (txreset_int & resetdone_tx);
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|
|
|
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// Output the PLL locked status
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assign plllkdet = cplllock;
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|
|
|
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// Report overall status for both transmitter and receiver reset done signals
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|
assign resetdone = cplllock ;
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|
|
|
|
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// reset to PCS part of GT
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|
assign pcsreset = !mmcm_locked;
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|
|
|
// temporary
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|
assign rxrundisp_int = 2'b0;
|
|
|
|
|
|
// Decode the GT transceiver buffer status signals
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|
always @(posedge usrclk2)
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|
begin
|
|
rxbuferr <= rxbufstatus_reg[2];
|
|
txbuferr <= txbufstatus_reg[1];
|
|
rxclkcorcnt <= {1'b0, rxclkcorcnt_int};
|
|
end
|
|
|
|
//---------------------------------------------------------------------------
|
|
// The core works from a 125MHz clock source userclk2, the init statemachines
|
|
// work at 200 MHz.
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Cross the clock domain
|
|
always @(posedge usrclk2)
|
|
begin
|
|
data_valid_reg <= data_valid;
|
|
end
|
|
|
|
|
|
gige_sfp_mdio_sync_block sync_block_data_valid
|
|
(
|
|
.clk (independent_clock),
|
|
.data_in (data_valid_reg),
|
|
.data_out (data_valid_reg2)
|
|
);
|
|
|
|
|
|
|
|
endmodule
|