Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
102 lines
3.6 KiB
Verilog
102 lines
3.6 KiB
Verilog
//------------------------------------------------------------------------------
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// File : gige_sfp_mdio_sync_block.vhd
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// Author : Xilinx Inc.
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//------------------------------------------------------------------------------
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// Description: Used on signals crossing from one clock domain to
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// another, this is a flip-flop pair, with both flops
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// placed together with RLOCs into the same slice. Thus
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// the routing delay between the two is minimum to safe-
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// guard against metastability issues.
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//------------------------------------------------------------------------------
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// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//------------------------------------------------------------------------------
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`timescale 1ps / 1ps
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module gige_sfp_mdio_sync_block #(
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parameter INITIALISE = 2'b00
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)
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(
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input clk, // clock to be sync'ed to
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input data_in, // Data to be 'synced'
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output data_out // synced data
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);
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// Internal Signals
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wire data_sync1;
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wire data_sync2;
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(* shreg_extract = "no", ASYNC_REG = "TRUE", RLOC = "X0Y0" *)
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FD #(
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.INIT (INITIALISE[0])
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) data_sync (
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.C (clk),
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.D (data_in),
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.Q (data_sync1)
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);
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(* shreg_extract = "no", RLOC = "X0Y0" *)
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FD #(
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.INIT (INITIALISE[1])
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) data_sync_reg (
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.C (clk),
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.D (data_sync1),
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.Q (data_sync2)
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);
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assign data_out = data_sync2;
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endmodule
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