Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
`timescale 1ps/1ps
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module gen_ddrlvds_tb();
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wire GSR, GTS;
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glbl glbl( );
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reg clk = 1;
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reg clk_2x = 1;
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reg reset = 1;
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reg sync_dacs_req = 0;
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always #100 clk = ~clk;
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always #50 clk_2x = ~clk_2x;
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wire [7:0] dac_pins_p, dac_pins_n;
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wire dac_frame_p, dac_frame_n;
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wire dac_clk_p, dac_clk_n;
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reg [7:0] count;
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wire [15:0] i = {4'hA,count};
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wire [15:0] q = {4'hB,count};
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initial
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begin
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#500 reset = 0;
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@(posedge clk);
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//#10
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sync_dacs_req <= 1;
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#200
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sync_dacs_req <= 0;
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// BURST (4);
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// BURST (5);
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#20000;
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end
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task BURST;
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input [7:0] len;
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begin
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sync_dacs_req <= 0;
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count <= 0;
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@ (posedge clk);
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@ (posedge clk);
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repeat (len)
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begin
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sync_dacs_req <= 1;
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@ (posedge clk);
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sync_dacs_req <= 0;
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@ (posedge clk);
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count <= count + 1;
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end
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sync_dacs_req <= 0;
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@ (posedge clk);
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@ (posedge clk);
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@ (posedge clk);
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end
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endtask //
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gen_ddrlvds dut (
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.reset(reset),
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.tx_clk_2x_p(dac_clk_p), .tx_clk_2x_n(dac_clk_n),
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.tx_frame_p(dac_frame_p), .tx_frame_n(dac_frame_n),
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.tx_d_p(dac_pins_p), .tx_d_n(dac_pins_n),
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.tx_clk_2x(clk_2x), .tx_clk_1x(clk),
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.i(i), .q(q),
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.sync_dacs(sync_dacs_req)
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);
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endmodule // gen_ddrlvds_tb
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