Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
10 lines
237 B
Plaintext
10 lines
237 B
Plaintext
SET busformat = BusFormatAngleBracketNotRipped
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SET designentry = Verilog
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SET device = xc7k325t
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SET devicefamily = kintex7
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SET flowvendor = Foundation_ISE
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SET package = ffg900
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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