92 lines
1.3 KiB
Verilog
92 lines
1.3 KiB
Verilog
wire fail;
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wire done;
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reg start;
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reg [15:0] control;
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axi_chdr_test_pattern axi_chdr_test_pattern_i
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(
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.clk(clk),
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.reset(reset),
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//
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// CHDR friendly AXI stream input
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//
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.i_tdata(i_tdata),
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.i_tlast(i_tlast),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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//
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// CHDR friendly AXI Stream output
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//
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.o_tdata(o_tdata),
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.o_tlast(o_tlast),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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//
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// Test flags
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//
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.start(start),
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.fail(fail),
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.done(done),
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.control(control)
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);
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always
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#5 clk <= ~clk;
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initial
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begin
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clk <= 1'b0;
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reset <= 1'b0;
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clear <= 1'b0;
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start <= 1'b0;
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control <= 16'h0101;
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@(negedge clk);
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reset <= 1'b1;
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repeat(10) @(negedge clk);
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reset <= 1'b0;
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repeat(10) @(negedge clk);
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// Now activate BIST
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start <= 1'b1;
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// Wait until simulation is done.
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while(!done)
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@(negedge clk);
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$display;
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if (fail)
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$display("FAILED.");
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else
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$display("Done 1st pass.");
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@(posedge clk);
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start <= 1'b0;
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repeat(10) @(negedge clk);
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// Now activate BIST
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start <= 1'b1;
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// Wait until simulation is done.
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while(!done)
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@(negedge clk);
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$display;
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if (fail)
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$display("FAILED.");
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else
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$display("PASSED.");
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$finish;
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end
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//initial
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// o_tready = 1;
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