Files
b210-k7-fpga/sim/axi_dram_fifo/sim_sram_1/run_isim
T
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

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vlogcomp -work work ${XILINX}/verilog/src/glbl.v
#vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../packet_proc/source_flow_control_tb.v
vlogcomp -work work --sourcelibext .v \
--sourcelibdir ../../../lib/axi \
--sourcelibdir ../../../lib/fifo \
--sourcelibdir ../../../lib/control \
--sourcelibdir ../../../top/x300/coregen \
../../../lib/axi/axi_dram_fifo_tb.v
fuse work.axi_dram_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_dram_fifo_tb.exe
# run the simulation scrip
./axi_dram_fifo_tb.exe # -gui #-tclbatch simcmds.tcl