143 lines
3.6 KiB
Verilog
143 lines
3.6 KiB
Verilog
//
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// Synthesizable Tx checker for 10G Ethernet MAC.
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// Generates deterministic packets that can be looped back and
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// checked for correctness
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//
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`define IDLE 0
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`define MAC1 1
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`define MAC2 2
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`define PAYLOAD1 3
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`define WAIT 4
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`define DONE 5
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module tx_checker
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(
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input clk156,
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input rst,
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input enable,
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output reg done,
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//
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output reg pkt_tx_val,
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output reg pkt_tx_sop,
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output reg pkt_tx_eop,
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output reg [2:0] pkt_tx_mod,
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output reg [63:0] pkt_tx_data
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);
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reg [10:0] payload;
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reg [10:0] count;
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reg [7:0] state;
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reg [9:0] delay;
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always @(posedge clk156)
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if (rst)
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begin
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state <= `IDLE;
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count <= 0;
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payload <= 45; // 1 less than ethernet minimum payload size.\
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done <= 0;
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delay <= 0;
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pkt_tx_val <= 0;
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pkt_tx_sop <= 0;
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pkt_tx_eop <= 0;
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pkt_tx_data <= 0;
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pkt_tx_mod <= 0;
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end
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else
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begin
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state <= state;
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pkt_tx_val <= 0;
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pkt_tx_sop <= 0;
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pkt_tx_eop <= 0;
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pkt_tx_data <= 0;
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pkt_tx_mod <= 0;
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payload <= payload;
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count <= count;
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done <= 0;
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delay <= delay;
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case(state)
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// Wait in IDLE state until enabled.
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// As we leave the idle state increment the payload count
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// so that we have a test pattern that changes each iteration.
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`IDLE: begin
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if (enable)
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begin
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if (payload == 1500)
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state <= `DONE;
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else
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begin
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payload <= payload + 1; // Might need to tweak this later..
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state <= `MAC1;
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end
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end
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end
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// Assert SOP (Start of Packet) for 1 cycle.
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// Assert VAL (Tx Valid) for duration of packet.
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// Put first 8 octets out, including
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// DST MAC addr and first 2 bytes of SRC MAC.
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`MAC1: begin
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pkt_tx_val <= 1;
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pkt_tx_sop <= 1;
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pkt_tx_data[63:16] <= 48'h0001020304; // DST MAC
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pkt_tx_data[15:0] <= 16'h0000; // SRC MAC msb's
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pkt_tx_mod <= 3'h0; // All octects valid
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state <= `MAC2;
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end
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// SOP now deasserted for rest of packet.
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// VAL remains asserted.
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// Tx rest of SRC MAC and ether type then first two data octets.
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`MAC2: begin
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pkt_tx_val <= 1;
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pkt_tx_data[63:32] <= 32'h05060708; // SRC MAC lsb's
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pkt_tx_data[31:16] <= 16'h88b5; // Ethertype
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pkt_tx_data[15:0] <= 16'hBEEF; // First 2 bytes of payload.
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pkt_tx_mod <= 3'h0; // All octects valid
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count <= payload - 2; // Preload counter for this packet
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state <= `PAYLOAD1;
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end
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// Iterate in this state until end of packet.
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// The first clock cycle in this state, SRC MAC and ETHERTYPE are being Tx'ed due to pipelining
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`PAYLOAD1: begin
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pkt_tx_val <= 1;
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pkt_tx_data <= {8{count[10:3]}}; // Data pattern is 64bit word count value.
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count <= count - 8;
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if ((count[10:3] == 0) || (count[10:0] == 8)) // down to 8 or less octects to Tx.
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begin
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pkt_tx_mod <= count[2:0];
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pkt_tx_eop <= 1;
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state <= `WAIT;
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delay <= 20; // 20 cycle delay in END state before Tx next packet
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end
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end // case: `PAYLOAD1
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// Because of pipelining EOP is actually asserted in this state
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// but we are already commited to the end of packet so no decisions need to be made.
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// Make signals idle ready for next state after.
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// Delay start of next packet to rate control test.
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`WAIT:begin
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delay <= delay - 1;
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if (delay == 0)
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state <= `IDLE;
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end
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// Have now transmitted one packet of every legal size (no jumbo frames)
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// Stay in this state asserting done flag until reset.
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`DONE:begin
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state <= `DONE;
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done <= 1;
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end
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endcase // case(state)
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end
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endmodule // tx_checker
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