206 lines
6.5 KiB
Verilog
206 lines
6.5 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "rx_dequeue.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module rx_dequeue(/*AUTOARG*/
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// Outputs
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rxdfifo_ren, pkt_rx_data, pkt_rx_val, pkt_rx_sop, pkt_rx_eop,
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pkt_rx_err, pkt_rx_mod, pkt_rx_avail, status_rxdfifo_udflow_tog,
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// Inputs
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clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
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rxdfifo_rempty, rxdfifo_ralmost_empty, pkt_rx_ren
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);
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input clk_156m25;
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input reset_156m25_n;
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input [63:0] rxdfifo_rdata;
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input [7:0] rxdfifo_rstatus;
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input rxdfifo_rempty;
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input rxdfifo_ralmost_empty;
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input pkt_rx_ren;
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output rxdfifo_ren;
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output [63:0] pkt_rx_data;
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output pkt_rx_val;
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output pkt_rx_sop;
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output pkt_rx_eop;
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output pkt_rx_err;
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output [2:0] pkt_rx_mod;
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output pkt_rx_avail;
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output status_rxdfifo_udflow_tog;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg pkt_rx_avail;
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reg [63:0] pkt_rx_data;
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reg pkt_rx_eop;
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reg pkt_rx_err;
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reg [2:0] pkt_rx_mod;
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reg pkt_rx_sop;
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reg pkt_rx_val;
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reg status_rxdfifo_udflow_tog;
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// End of automatics
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reg end_eop;
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/*AUTOWIRE*/
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// End eop to force one cycle between packets
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assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop;
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always @(posedge clk_156m25 or negedge reset_156m25_n) begin
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if (reset_156m25_n == 1'b0) begin
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pkt_rx_avail <= 1'b0;
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pkt_rx_data <= 64'b0;
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pkt_rx_sop <= 1'b0;
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pkt_rx_eop <= 1'b0;
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pkt_rx_err <= 1'b0;
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pkt_rx_mod <= 3'b0;
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pkt_rx_val <= 1'b0;
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end_eop <= 1'b0;
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status_rxdfifo_udflow_tog <= 1'b0;
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end
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else begin
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pkt_rx_avail <= !rxdfifo_ralmost_empty;
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// If eop shows up at the output of the fifo, we drive eop on
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// the bus on the next read. This will be the last read for this
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// packet. The fifo is designed to output data early. On last read,
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// data from next packet will appear at the output of fifo. Modulus
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// of packet length is in lower bits.
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pkt_rx_eop <= rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP];
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pkt_rx_mod <= {3{rxdfifo_ren & rxdfifo_rstatus[`RXSTATUS_EOP]}} & rxdfifo_rstatus[2:0];
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pkt_rx_val <= rxdfifo_ren;
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if (rxdfifo_ren) begin
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`ifdef BIGENDIAN
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pkt_rx_data <= {rxdfifo_rdata[7:0],
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rxdfifo_rdata[15:8],
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rxdfifo_rdata[23:16],
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rxdfifo_rdata[31:24],
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rxdfifo_rdata[39:32],
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rxdfifo_rdata[47:40],
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rxdfifo_rdata[55:48],
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rxdfifo_rdata[63:56]};
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`else
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pkt_rx_data <= rxdfifo_rdata;
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`endif
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end
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if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_SOP]) begin
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// SOP indication on first word
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pkt_rx_sop <= 1'b1;
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pkt_rx_err <= 1'b0;
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end
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else begin
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pkt_rx_sop <= 1'b0;
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// Give an error if FIFO is to underflow
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if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
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pkt_rx_val <= 1'b1;
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pkt_rx_eop <= 1'b1;
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pkt_rx_err <= 1'b1;
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end
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end
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if (rxdfifo_ren && |(rxdfifo_rstatus[`RXSTATUS_ERR])) begin
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// Status stored in FIFO is propagated to error signal.
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pkt_rx_err <= 1'b1;
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end
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//---
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// EOP indication at the end of the frame. Cleared otherwise.
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if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_EOP]) begin
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end_eop <= 1'b1;
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end
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else if (pkt_rx_ren) begin
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end_eop <= 1'b0;
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end
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//---
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// FIFO errors, used to generate interrupts
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if (rxdfifo_rempty && pkt_rx_ren && !end_eop) begin
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status_rxdfifo_udflow_tog <= ~status_rxdfifo_udflow_tog;
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end
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end
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end
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endmodule
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