49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module ll8_to_txmac
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(input clk, input reset, input clear,
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input [7:0] ll_data, input ll_eof, input ll_src_rdy, output ll_dst_rdy,
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output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack );
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reg [2:0] xfer_state;
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localparam XFER_IDLE = 0;
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localparam XFER_ACTIVE = 1;
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localparam XFER_WAIT1 = 2;
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localparam XFER_UNDERRUN = 3;
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localparam XFER_DROP = 4;
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always @(posedge clk)
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if(reset | clear)
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xfer_state <= XFER_IDLE;
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else
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case(xfer_state)
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XFER_IDLE :
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if(tx_ack)
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xfer_state <= XFER_ACTIVE;
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XFER_ACTIVE :
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if(~ll_src_rdy)
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xfer_state <= XFER_UNDERRUN;
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else if(ll_eof)
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xfer_state <= XFER_WAIT1;
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XFER_WAIT1 :
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xfer_state <= XFER_IDLE;
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XFER_UNDERRUN :
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xfer_state <= XFER_DROP;
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XFER_DROP :
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if(ll_eof)
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xfer_state <= XFER_IDLE;
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endcase // case (xfer_state)
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assign ll_dst_rdy = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP);
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assign tx_valid = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE);
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assign tx_data = ll_data;
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assign tx_error = (xfer_state == XFER_UNDERRUN);
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endmodule // ll8_to_txmac
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