45 lines
1.4 KiB
Verilog
45 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// TX side of flow control -- when other side sends PAUSE, we wait
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module flow_ctrl_tx
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(input rst,
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input tx_clk,
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//host processor
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input tx_pause_en,
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// From MAC_rx_ctrl
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input [15:0] pause_quanta,
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input pause_quanta_val,
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// MAC_tx_ctrl
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output pause_apply,
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input paused);
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// ******************************************************************************
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// Inhibit our TX from transmitting because they sent us a PAUSE frame
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// ******************************************************************************
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// Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
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// as big as 16 bits, so 22 bits are needed for the counter
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reg [15+6:0] pause_quanta_counter;
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reg pqval_d1, pqval_d2;
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always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
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always @(posedge tx_clk) pqval_d2 <= pqval_d1;
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always @ (posedge tx_clk or posedge rst)
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if (rst)
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pause_quanta_counter <= 0;
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else if (pqval_d1 & ~pqval_d2)
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pause_quanta_counter <= {pause_quanta, 6'b0};
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else if((pause_quanta_counter!=0) & paused)
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pause_quanta_counter <= pause_quanta_counter - 1;
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assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
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endmodule // flow_ctrl
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