Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
24 lines
553 B
Makefile
24 lines
553 B
Makefile
#
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# Copyright 2013 Ettus Research LLC
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#
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##################################################
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# Packet Processing Sources
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##################################################
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PACKET_PROC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/packet_proc/, \
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eth_dispatch.v \
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ip_hdr_checksum.v \
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vrlp_eth_framer.v \
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chdr_eth_framer.v \
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eth_interface.v \
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vrlp_to_compressed_vita.v \
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compressed_vita_to_vrlp.v \
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source_flow_control.v \
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cvita_insert_tlast.v \
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cvita_dest_lookup.v \
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cvita_chunker.v \
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cvita_dechunker.v \
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axis_packet_debug.v \
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cvita_packet_debug.v \
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))
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