27 lines
499 B
Verilog
27 lines
499 B
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module pcie_lossy_samp_gate
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(
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input [63:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [63:0] o_tdata,
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output o_tvalid,
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input o_tready,
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input drop,
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output dropping
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);
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assign o_tdata = i_tdata;
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assign o_tvalid = i_tvalid & ~drop;
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assign i_tready = o_tready | drop;
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assign dropping = drop & i_tvalid;
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endmodule // pcie_lossy_samp_gate
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