23 lines
784 B
Verilog
23 lines
784 B
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module data_swapper_64 (
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input [2:0] swap_lanes,
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input [63:0] i_tdata,
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output [63:0] o_tdata
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);
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localparam SWAP_32B = 3'b100;
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localparam SWAP_16B = 3'b010;
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localparam SWAP_8B = 3'b001;
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wire [63:0] data_p1, data_p2;
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assign data_p1 = (|(swap_lanes & SWAP_32B)) ? { i_tdata[31:0], i_tdata[63:32] } : i_tdata;
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assign data_p2 = (|(swap_lanes & SWAP_16B)) ? { data_p1[47:32], data_p1[63:48], data_p1[15:0], data_p1[31:16] } : data_p1;
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assign o_tdata = (|(swap_lanes & SWAP_8B)) ? { data_p2[55:48], data_p2[63:56], data_p2[39:32], data_p2[47:40],
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data_p2[23:16], data_p2[31:24], data_p2[7:0], data_p2[15:8] } : data_p2;
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endmodule // data_swapper_64
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