98 lines
3.1 KiB
Verilog
98 lines
3.1 KiB
Verilog
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module tx_frontend
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#(parameter BASE=0,
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parameter WIDTH_OUT=16,
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parameter IQCOMP_EN=1)
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(input clk, input rst,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [23:0] tx_i, input [23:0] tx_q, input run,
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output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b
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);
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// IQ balance --> DC offset --> rounding --> mux
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wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
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wire [WIDTH_OUT-1:0] i_final, q_final;
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wire [7:0] mux_ctrl;
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wire [35:0] corr_i, corr_q;
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wire [23:0] i_bal, q_bal;
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wire [17:0] mag_corr, phase_corr;
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setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(i_dco),.changed());
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setting_reg #(.my_addr(BASE+1), .width(24)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(q_dco),.changed());
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setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(mag_corr),.changed());
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setting_reg #(.my_addr(BASE+3),.width(18)) sr_3
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_corr),.changed());
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setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(mux_ctrl),.changed());
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generate
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if(IQCOMP_EN==1)
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begin
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// IQ Balance
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MULT18X18S mult_mag_corr
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(.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) );
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MULT18X18S mult_phase_corr
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(.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
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add2_and_clip_reg #(.WIDTH(24)) add_clip_i
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(.clk(clk), .rst(rst),
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.in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1),
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.sum(i_bal), .strobe_out());
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add2_and_clip_reg #(.WIDTH(24)) add_clip_q
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(.clk(clk), .rst(rst),
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.in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1),
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.sum(q_bal), .strobe_out());
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end // if (IQCOMP_EN==1)
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else
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begin
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assign i_bal = tx_i;
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assign q_bal = tx_q;
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end // else: !if(IQCOMP_EN==1)
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endgenerate
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// DC Offset
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add2_and_clip_reg #(.WIDTH(24)) add_dco_i
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(.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
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add2_and_clip_reg #(.WIDTH(24)) add_dco_q
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(.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
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// Rounding
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round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i
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(.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
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round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
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(.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
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// Mux
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always @(posedge clk)
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case(mux_ctrl[3:0])
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0 : dac_a <= i_final;
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1 : dac_a <= q_final;
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default : dac_a <= 0;
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endcase // case (mux_ctrl[3:0])
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always @(posedge clk)
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case(mux_ctrl[7:4])
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0 : dac_b <= i_final;
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1 : dac_b <= q_final;
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default : dac_b <= 0;
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endcase // case (mux_ctrl[7:4])
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endmodule // tx_frontend
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