26 lines
535 B
Verilog
26 lines
535 B
Verilog
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module add2_and_clip_reg
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#(parameter WIDTH=16)
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(input clk,
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input rst,
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input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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input strobe_in,
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output reg [WIDTH-1:0] sum,
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output reg strobe_out);
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wire [WIDTH-1:0] sum_int;
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add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
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always @(posedge clk)
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if(rst)
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sum <= 0;
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else if(strobe_in)
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sum <= sum_int;
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always @(posedge clk)
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strobe_out <= strobe_in;
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endmodule // add2_and_clip_reg
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