miegl/b210-k7-fpga
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b210-k7-fpga/top/e31x
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Wade Fife 28955fb9f4 fpga: e31x: Change RFNoC Ctrl clock to 40 MHz 
Original-commit: 8622a8013a429674de59cbff522b2722c8afa449
2020-08-19 12:28:22 -05:00
..
dts
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ip
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
sim
fpga: rfnoc: Fix testbenches to run under ModelSim
2020-07-20 15:33:22 -05:00
.gitignore
fpga: e31x: Add gitignore file
2020-07-18 13:33:42 -05:00
axi_pmu.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_e31x.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_core.v
fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
2020-08-19 12:28:22 -05:00
e31x_idle_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_idle.v
e31x: Swap out liberio for internal ethernet in the idle image
2020-07-18 11:52:58 -05:00
e31x_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_rfnoc_image_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_rfnoc_image_core.yml
fpga: e310: Fix device in image core YAML
2020-08-14 15:11:08 -05:00
e31x_timing.xdc
fpga: e31x: Update constraints to avoid timing issues
2020-04-08 17:24:15 -05:00
e31x.v
fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
2020-08-19 12:28:22 -05:00
e310_io.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e310_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.e31x.inc
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ppsloop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
spi_slave.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00