165 lines
5.3 KiB
Makefile
165 lines
5.3 KiB
Makefile
#
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# Copyright 2014-2015 Ettus Research
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#
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# -------------------------------------------------------------------
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# Mode switches
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# -------------------------------------------------------------------
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# Calling with FAST:=1 will switch to using unifast libs
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ifeq ($(FAST),1)
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SIM_FAST=true
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else
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SIM_FAST=false
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endif
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# -------------------------------------------------------------------
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# Variables
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# -------------------------------------------------------------------
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ifdef SIM_COMPLIBDIR
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COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR))
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endif
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# Get full part name, formatted for Vivado
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PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(ARCH)/$(PART_ID)`
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# Resolve path
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EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS))
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EXP_SIM_SRCS = $(call RESOLVE_PATHS,$(SIM_SRCS))
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EXP_INC_SRCS = $(call RESOLVE_PATHS,$(INC_SRCS))
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# Working directory for native ModelSim execution
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MODELSIM_PROJ_DIR ?= modelsim_proj
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# -------------------------------------------------------------------
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# Usage: SETUP_AND_LAUNCH_SIMULATION
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# Args: $1 = Simulator Name
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# -------------------------------------------------------------------
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SETUP_AND_LAUNCH_SIMULATION = \
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@ \
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export VIV_SIMULATOR=$1; \
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export VIV_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \
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export VIV_SIM_SRCS=$(EXP_SIM_SRCS); \
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export VIV_INC_SRCS=$(EXP_INC_SRCS); \
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export VIV_SIM_TOP=$(SIM_TOP); \
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export VIV_SYNTH_TOP="$(SYNTH_DUT)"; \
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export VIV_PART_NAME=$(PART_NAME); \
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export VIV_SIM_RUNTIME=$(SIM_RUNTIME_US); \
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export VIV_SIM_FAST="$(SIM_FAST)"; \
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export VIV_SIM_COMPLIBDIR=$(COMPLIBDIR); \
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export VIV_SIM_USER_DO=$(MODELSIM_USER_DO); \
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export VIV_MODE=$(VIVADO_MODE); \
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export VIV_SIM_64BIT=$(MODELSIM_64BIT); \
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export VIV_VERILOG_DEFS="UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
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$(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal
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# -------------------------------------------------------------------
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# Usage: SETUP_AND_LAUNCH_VCOM
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# Args: N/A
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# -------------------------------------------------------------------
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SETUP_AND_LAUNCH_VCOM = \
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@ \
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export VCOM_PROJ_DIR=$(MODELSIM_PROJ_DIR); \
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export VCOM_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \
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export VCOM_SIM_SRCS=$(EXP_SIM_SRCS); \
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export VCOM_INC_SRCS=$(EXP_INC_SRCS); \
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export VCOM_SVLOG_ARGS="$(SVLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
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export VCOM_VLOG_ARGS="$(VLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
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export VCOM_VHDL_ARGS="$(VHDL_ARGS)"; \
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export VCOM_MODELSIM_INI="$(MODELSIM_INI)"; \
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$(TOOLS_DIR)/scripts/launch_vcom.sh
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# -------------------------------------------------------------------
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# Usage: SETUP_AND_LAUNCH_MODELSIM
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# Args: N/A
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# -------------------------------------------------------------------
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SETUP_AND_LAUNCH_MODELSIM = \
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@ \
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export MSIM_PROJ_DIR=$(MODELSIM_PROJ_DIR); \
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export MSIM_SIM_TOP="$(SIM_TOP)"; \
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export MSIM_ARGS="$(MODELSIM_ARGS)"; \
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export MSIM_LIBS="$(MODELSIM_LIBS)"; \
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export MSIM_MODE=$(VIVADO_MODE); \
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export MSIM_MODELSIM_INI="$(MODELSIM_INI)"; \
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export MSIM_VARIANT=legacy; \
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$(TOOLS_DIR)/scripts/launch_modelsim.sh
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# -------------------------------------------------------------------
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# Usage: SETUP_AND_LAUNCH_QUESTASIM
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# Args: N/A
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# -------------------------------------------------------------------
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SETUP_AND_LAUNCH_QUESTASIM = \
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@ \
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export MSIM_GUI=visualizer; \
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export MSIM_PROJ_DIR=$(MODELSIM_PROJ_DIR); \
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export MSIM_SIM_TOP="$(SIM_TOP)"; \
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export MSIM_ARGS="$(MODELSIM_ARGS)"; \
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export MSIM_LIBS="$(MODELSIM_LIBS)"; \
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export MSIM_MODE=$(VIVADO_MODE); \
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export MSIM_MODELSIM_INI="$(MODELSIM_INI)"; \
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export MSIM_VARIANT=questa; \
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$(TOOLS_DIR)/scripts/launch_modelsim.sh
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.SECONDEXPANSION:
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##ip: Generate the IP required for this simulation
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ip: $(DESIGN_SRCS)
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##xsim: Run the simulation using the Xilinx Vivado Simulator
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xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(call SETUP_AND_LAUNCH_SIMULATION,XSim)
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##xclean: Cleanup Xilinx Vivado Simulator intermediate files
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xclean:
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@rm -f xsim*.log
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@rm -rf xsim_proj
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@rm -f xvhdl.log
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@rm -f xvhdl.pba
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@rm -f xvlog.log
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@rm -f xvlog.pb
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@rm -f vivado_pid*.str
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##vsim: Run the simulation using ModelSim from inside Vivado
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vsim: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(call SETUP_AND_LAUNCH_SIMULATION,Modelsim)
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##qsim: Run the simulation using Questa
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qsim: .check_tool vlint
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$(call SETUP_AND_LAUNCH_QUESTASIM)
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##msim: Run the simulation using ModelSim
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msim: .check_tool vlint
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$(call SETUP_AND_LAUNCH_MODELSIM)
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# Alias for msim (for backwards compatibility)
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modelsim: msim
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# NOTE: VHDL files require a correct compile order. This script compiles files
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# in the order they are defined in $(DESIGN_SRC), then $SIM_SRC)
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##vcom: Run ModelSim/Questa compiler to compile HDL files
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vcom: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
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$(call SETUP_AND_LAUNCH_VCOM)
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# Alias for vcom (for backwards compatibility)
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vlint: vcom
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##vclean: Cleanup ModelSim/Questa intermediate files
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vclean:
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@rm -f modelsim*.log
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@rm -rf $(MODELSIM_PROJ_DIR)
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@rm -f vivado_pid*.str
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# Use clean with :: to support allow "make clean" to work with multiple makefiles
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clean:: xclean vclean
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help::
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@grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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.PHONY: ip xsim xsim_hls xclean vsim vlint vclean clean help
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