Wade Fife
4f99fee248
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its (X,Y) inputs and its magnitude output. So, having 17 bits means we have enough precision to represent the entire range of an sc16. The 16-bit CORDIC is insufficient to cover this entire range. Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
73 lines
2.5 KiB
Makefile
73 lines
2.5 KiB
Makefile
#
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# Copyright 2016 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(LIB_IP_DIR)/axi_fft/Makefile.inc
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include $(LIB_IP_DIR)/axi_hb31/Makefile.inc
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include $(LIB_IP_DIR)/axi_hb47/Makefile.inc
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include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
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include $(LIB_IP_DIR)/complex_to_magphase_int17/Makefile.inc
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include $(LIB_IP_DIR)/complex_to_magphase_int16_int24/Makefile.inc
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include $(LIB_IP_DIR)/complex_to_magphase_int32/Makefile.inc
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include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/cordic_rotator/Makefile.inc
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include $(LIB_IP_DIR)/cordic_rotator24/Makefile.inc
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include $(LIB_IP_DIR)/cordic_rotate_int24_int16/Makefile.inc
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include $(LIB_IP_DIR)/cordic_rotate_int24/Makefile.inc
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include $(LIB_IP_DIR)/divide_int16/Makefile.inc
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include $(LIB_IP_DIR)/divide_int24/Makefile.inc
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include $(LIB_IP_DIR)/divide_int32/Makefile.inc
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include $(LIB_IP_DIR)/divide_uint32/Makefile.inc
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include $(LIB_IP_DIR)/divide_int16_int32/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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LIB_IP_XCI_SRCS = \
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$(LIB_IP_AXI_FFT_SRCS) \
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$(LIB_IP_AXI_HB31_SRCS) \
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$(LIB_IP_AXI_HB47_SRCS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_CORDIC_ROTATOR_SRCS) \
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$(LIB_IP_CORDIC_ROTATOR24_SRCS) \
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$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) \
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$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) \
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$(LIB_IP_DIVIDE_INT16_SRCS) \
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$(LIB_IP_DIVIDE_INT24_SRCS) \
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$(LIB_IP_DIVIDE_INT32_SRCS) \
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$(LIB_IP_DIVIDE_UINT32_SRCS) \
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$(LIB_IP_DIVIDE_INT16_INT32_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS)
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LIB_IP_SYNTH_OUTPUTS = \
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$(LIB_IP_AXI_FFT_OUTS) \
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$(LIB_IP_AXI_HB31_OUTS) \
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$(LIB_IP_AXI_HB47_OUTS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) \
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_OUTS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) \
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$(LIB_IP_CORDIC_ROTATOR_OUTS) \
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$(LIB_IP_CORDIC_ROTATOR24_OUTS) \
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$(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS) \
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$(LIB_IP_CORDIC_ROTATE_INT24_OUTS) \
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$(LIB_IP_DIVIDE_INT16_OUTS) \
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$(LIB_IP_DIVIDE_INT24_OUTS) \
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$(LIB_IP_DIVIDE_INT32_OUTS) \
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$(LIB_IP_DIVIDE_UINT32_OUTS) \
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$(LIB_IP_DIVIDE_INT16_INT32_OUTS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS)
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lib_ip: $(LIB_IP_SYNTH_OUTPUTS)
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.PHONY: lib_ip
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