61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: capture_sysref
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//
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// Description:
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//
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// Capture SYSREF and transfer it to the higher clock domain. Module incurs
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// in 2 pll_ref_clk cycles + 1 rfdc_clk cycle of delay.
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//
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module capture_sysref (
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// Clocks
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input wire pll_ref_clk,
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input wire rfdc_clk,
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// SYSREF input and control
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input wire sysref_in, // Single-ended SYSREF (previously buffered)
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input wire enable_rclk, // Enables SYSREF output in the rfdc_clk domain.
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// Captured SYSREF outputs
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output wire sysref_out_pclk, // Debug output (Domain: pll_ref_clk).
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output wire sysref_out_rclk // RFDC output (Domain: rfdc_clk).
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);
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reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;
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// Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
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// in case static timing isn't met so as not to destroy downstream logic.
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always @ (posedge pll_ref_clk) begin
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sysref_pclk_ms <= sysref_in;
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sysref_pclk <= sysref_pclk_ms;
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end
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assign sysref_out_pclk = sysref_pclk;
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// Transfer to faster clock which is edge-aligned with the pll_ref_clk.
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always @ (posedge rfdc_clk) begin
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if (enable_rclk) begin
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sysref_rclk <= sysref_pclk;
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end else begin
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sysref_rclk <= 1'b0;
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end
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end
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assign sysref_out_rclk = sysref_rclk;
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endmodule
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